本篇論文之重點主要在研究以矽為基底的矽鍺異質接面雙載子電晶體的雜訊特性以及幾何結構效應的分析，進而在一既定製程下，如何利用幾何結構的分析進而找到一最佳化的高頻雜訊效應，並且實際設計出低雜訊放大器，以便驗證所提出的最佳化低雜訊元件與方法是確實可行。對於設計低雜訊放大器，必須要盡量把雜訊指數與增益盡量調到最佳化。此外，由於矽基板對於電路的高頻訊號有極嚴重的影響，因此，也必須盡量減少整體電路用於匹配的被動元件，以便降低受到矽基板的影響，並減低整體面積。因此，在本篇論文就針對矽鍺異質接面雙載子電晶體的幾何結構去做探討與改良，並且也對所加的偏壓做最佳化，以求得最佳的雜訊特性。在高頻雜訊分析中，幾何結構的效應證實了一個矽鍺異質接面雙載子電晶體若能有較長的射極長度以及多指結構，即能在高頻頻段的操作下有較佳的雜訊特性。並且分別在不同頻率與偏壓下，分別求出最佳化的元件大小。而針對多頻帶（2.4 GHz 與5 GHz 頻帶）的應用，也設計出一矽鍺異質接面雙載子電晶體的低雜訊放大器，並且其量測特性也符合所預定之規範。
此外，對於大訊號功率放大器的設計，也會先針對功率放大器的最主要的部分 – 功率電晶體 – 去做最佳化的探討與設計，以便減少受到一些非理想效應的干擾而降低了功率電晶體的功率輸出特性。最初先求得最佳的元件射極寬度，然後分別設計三種不同架構的功率電晶體，並利用負載拉移的方法去找出最佳阻抗點。經由大訊號的功率量測與線性度量測結果，最後證實在本論文所提出的改良型架構的確能有效減少非理想效應的干擾而降低功率電晶體的特性劣化程度。此外，此功率電晶體的輸出特性也符合5.2 GHz 無線區域網路系統所預定的規範。最後再利用這經過最佳化的功率電晶體去實現一個應用於5.2 GHz 無線區域網路的功率放大器，並且也同時驗證本論文所設計的功率電晶體的確是可以實際應用於功率放大器的電路設計。

In this dissertation, the RF noise and large signal power characteristics of SiGe HBTs are discussed, and the SiGe HBT multi-band low noise amplifier and the SiGe HBT power amplifier are designed for the WLAN application.
When HBTs are employed in the LNA, more attention should be paid to the noise figure (NF) and the associated available gain (GA,assoc) , and therefore the geometry and bias need to be optimized for the LNA design. Since substrate and interconnect losses are considerably higher in Si, the attention should be focused on optimizing the sizes of transistors to simplify the matching circuit. Therefore, the real part of the optimum source impedance (Re(Zopt)) of a transistor close to 50 Ω is selected for designing a Si-base LNA. In this way, the loss and even the chip area can be reduced.
The device dimension dependence of the performance indicates that there exists an optimum emitter length for the best RF noise performance. The suitable layout configuration and geometry of the device with better noise performance are determined and optimized in this work. The geometrical scaling including emitter length scaling and stripe number scaling can be adopted to optimize the emitter geometry to minimize losses of the matching network and overall noise figure. This method for designing LNA guarantees optimum noise and input impedance matching simultaneously with the simplest matching network. It is valid via the comparison of the state-of-the-art SiGe LNAs that the method of geometrical scaling for designing LNA with the simplest matching network is effective to obtain the better performances.
For Low-noise amplifier design, the emitter total length must be adjusted such that the real part of the optimum impedance (1/Ys,opt) equals 50 Ω. Using the geometrical scaling including length scaling and stripe number scaling to optimize the emitter geometry to minimize the matching circuit losses and overall noise figure. This method not only can choose a device, which can match 50 Ω very well, it can also select a device with smaller minimum noise figure, which will improve the noise performance. In actual LNA design, for a given bias current and device geometry, emitter and base inductances are added and the values of them are optimized to match a 50 Ω source impedance. Using this method, the optimal device sizes at f = 2.4 and 5.7 GHz, and JC = 0.1 and 0.2 mA/μm2 for LNA applications are summarized.
In this work, a two-stage cascade concurrent multi-band LNA has been designed. The input-matching network is the combination of parallel LC tank connection with series LC branch, and resistive shunt-shunt feedback is used at the second for wideband matching at the output. Using the parallel and series LC well to make the multi-band matching. The measured results shown that this LNA is suitable for multi-band wireless LAN application.
Since the PA is the most essential component in the RF transceiver, and the power cell determines the performance of the PA, hence, it’s very important to design a power cell with high power-added efficiency (PAE), power gain (GP), and linearity. Therefore, considering temperature effects and the desired high power level, it’s required to carefully design the layout of a power cell to maintain adequate gain and PAE. Due to the PA needs greater output power (Pout), the power cell of the PA is composed of an array of multifinger subcells. However, to make a power cell without careful design will induce non-ideal effects including thermal effects and inter-subcell phasing effects. There are some basic and familiar styles of power cells shown in literatures. However, these styles of power cells are still suffered from non-ideal effects. Hence, the objective in this work is to design an optimized and novel power cell with better performance than these styles of power cells.
Initially, a subcell with optimum emitter stripe width is designed. To choose the optimized power cell in respect of Pout, PAE and linearity, several power cells with the same numbers of subcells but different geometry are compared with each other. With the proposed way, the connection configuration of power cell type III is optimized for better performance. The full characterisation of SiGe HBTs power cells type I~III at 5.2 GHz in terms of DC characteristics, Pout, PAE and linearity are demonstrated. The experimental results clearly shown that the novel power cell type III with better performance can be employed in PAs for 802.11a WLAN applications. Moreover, this proposed power cell is designed to be suitable for circuit-level combination in PAs for WLAN IEEE 802.11a applications. Finally, this proposed power cell is used in designing a single-stage power amplifier to verify the feasibility of this proposed power cell for the 5.2 GHz WLAN IEEE 802.11a applications. After performing the load-pull measurement to obtain the optimum impedance, input and output matching networks can be constructed to achieve the optimum power performance. This single-stage SiGe HBT MMIC power amplifier for the IEEE 802.11a is designed with the proposed power cell, and performances of these key parameters meet the design specification at 5.2 GHz IEEE 802.11a bands.

[1.1] Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.
[1.2] Shiming Zhang et al., “The Effects of Geometrical Scaling on the Frequency Response and Noise Performance of SiGe HBTs,” IEEE Trans. Electron Devices, vol. 49 Issue: 3, pp.429-435, 2002.

[2.1] B.K. Oyama, and B.P Wong “GaAs HBT’s for analog circuits” Proceedings of the IEEE, vol. 81, pp. 1744-1761, Dec. 1993
[2.2] B.Bayraktaroglu “GaAs HBT’s for Microwave Integrated Circuit” Proceedings of the IEEE, vol. 81, pp. 1762-1785, Dec. 1993.
[2.3] I. Davies, R.A. Davies, S.P. March, N.A. Peniket, S.D. Wadsworth and R.H. Wallis, “GaAa/InGaP HBT Device and Circuit” Workshop on High Performance Electron Devices for Microwave and Optoelectronic Applications (IEEE EDMO), Nov. 1997, pp. 33-38
[2.4] Peter Ashburn, SiGe Heterojunction Bipolar Transistors. New York: John Wiley, 2003.
[2.5] J. Graul, H. Kaiser, W. Wilhelm and H. Ryssel, “Bipolar high-speed, low power gates with double implanted transistors,” IEEE J. Solid State Circuits, vol. 10, pp. 201-204, 1975.
[2.6] J. Graul, A. Glasl and H. Murrmann, “High performance transistors with arsenic-implanted polysil emitters,” IEEE J. Solid State Circuits, vol. 11, pp. 491-495, 1976.
[2.7] T.H. Ning, R.D. Isaac, P.M. Solomon, D.D. Tang, H. Yu, G.C. Feth and S.K. Wiedmann, “Self-aligned bipolar transistors for high-performance and low power delay VLSI,” IEEE Trans. Electron. Devices, vol. 28, pp. 1010-1013, 1981.
[2.8] J. Bock, H. Knapp, K. Aufinger, M. Wurzer, S. Boguth, R. Schreiter, T.F. Meister, M. Rest, M. Ohnemus, L. Treitinger, “12 ps implanted base silicon bipolar technology,” in IEEE IEDM Technical Digest, Dec. 1999, pp. 553-556.
[2.9] H. Higuchi, G. Kitsukawa, T. Ikeda, Y. Nishio, N. Sasaki and J. Ogiue, “Performance and structures of scaled-down bipolar devices merged with CMOSFETS,” in IEEE IEDM Technical Digest, Dec. 1984, pp. 694-697.
[2.10] S. Krishna, J. Kuo and I.S. Gaeta, “An analog technology integrates bipolar, CMOS, and high voltage DMOS transistors,” IEEE Trans. Electron. Devices, vol. 31, pp. 89-95, 1984.
[2.11] G.L. Paton, S.S. Iyer, S.L. Delage, S. Tiwari and J.M.C. Stork, “Silicon germanium base heterojunction bipolar transistors by molecular beam epitaxy,” IEEE Electron. Device Lett., vol. 9, pp. 165-167, 1988.
[2.12] C.A. King, J.L. Hoyt, C.M. Gronet, J.F. Gibbons, M.P. Scott and J. Turner, “Si/SiGe heterojunction bipolar transistors by limited reaction processing,” IEEE Electron. Device Lett.,vol. 10, pp. 52-54, 1989.
[2.13] D.L. Harame, J.H. Comfort, J.D. Cressler, E.F. Crabb´e, J.Y.C. Sun, B.S. Meyerson and T. Tice, “Si/SiGe epitaxial base transistors,” IEEE Trans. Electron. Devices, vol. 42, pp. 455-482, 1995.
[2.14] J.-S. Rieh, B. Jagannathan, H.Chen, K.T. Schonenberg, D. Angell, A. Chinthakindi, J. Florkey, F. Golan, D. Greenberg, S.-J. Jeng, M. Khater, F. Pagette, C. Schnabel, P. Smith, A. Stricker, K. Vaed, R. Volant, D. Ahlgren, G. Freeman, K. Stein, and S. Subbanna,, ‘SiGe HBTs with cut-off frequency of 350 GHz,” in IEEE IEDM Technical Digest, 2002, pp. 771-774.
[2.15] Frank Schwierz and Juin.J. Liou, “Modern Microwave Transistors” Theory, Design, and Performance, Chapter 8.
[2.16] S. S. Iyer, G. L. Patton, S. L. Delage, S. Tiwari, and J. M. C. Storck, Silicon-Germanium Base Heterojunction Bipolar Transistors by Molecular Beam Epitaxy, IEDM Tech. Dig., pp. 874-877, 1987.
[2.17] S. J. Jeng, B. Jagannathan, J.-S. Rieh, J. Johnson, K. T. Schonenberg, D.Greenberg, A. Stricker, H. Chen, M. Khater, D. Ahlgreen, G. Freeman, K. Stein, and S. Subbanna, A 210-GHz fT SiGe HBT with a Non-Self-Aligned Structure, IEEE Electron Device Lett., 22, pp. 542-544, 2001.
[2.18] C. A. King, M. R. Frei, M. Mastrapasqua, K. K. Ng, Y. O. Kim, R. W. Johnson, S. Moinian, S. Martin, H.-I. Cong, F. P. Klemens, R. Tang, D. Nguyen, T.-I. Hsu, T. Campbell, S. J. Molloy, L. B. Fritzinger, T. G. Ivanov, K. K. Bourdelle, C. Lee, Y. -F. Chyan, M. S. Carroll, and C. W. Leung, Very Low Cost Graded SiGe Base Bipolar Transistors for a High Performance Modular BiCMOS Process, IEDM Tech. Dig., pp. 565-568, 1999.
[2.19] J.A.del Alamo, and R.M. Swanson, “Forward biased tunnelling: a limitation to bipolar device scaling,” IEEE Electron. Device Lett., vol. 7, pp. 629-631, 1986.
[2.20] R. Lodge, “Advantages of SiGe for GSM RF front ends,” Electron. Eng., vol. 71, no. 865, pp. 18–19, Feb. 1999. (UK).
[2.21] R. Gotsfried, F. Beisswanger, S. Gerlach, A. Schuppen, H. Dietrich, U. Seiler, K. H. Bach, and J. Albers, “RFIC’s for mobile communication systems using SiGe bipolar technology,” IEEE Trans. Microwave Theory, Tech., pt. 2, vol. 46, pp. 661–668, May 1998.
[2.22] M. Racanelli, Z. Zhang, J. Zhang, A. Kar-Roy, P. Joshi, A. Kalbureg, L. Nathawad, M. Todd, C. Ukah, C. Hu, C. Compton, K. Schuegraf, P. Ye, R. Dowlatshahi, G. Jolly, and P. Kempf, “BC35: A 0.35 μm 30 GHz, production RF BiCMOS technology,” in Proc. 1999 BCTM, 1999, pp. 125–128.
[2.23] C. A. King, M. R. Frei, M. Mastrapasqua, K. K. Ng, Y. O. Kim, R. W. Johnson, S. Moinian, S. Martin, K.-I. Cong, F. P. Klemens, R. Tang, D. Nguyen, T.-I. Hsu, T. Campbell, S. J. Molloy, L. B. Fritzinger, T. G. Ivanov, K. K. Bourdelle, C. Lee, Y.-F. Chyan, M. S. Carroll, and C. W. Leung, “Very low colst graded SiGe base bipolar transistors for a high performance modular BiCMOS process,” in Proc. 1999 IEDM, 1999, pp. 565–568.
[2.24] A. Chantre, M. Marty, J. L. Regolini, M. Mouis, J. de Pontcharra, D. Dutartre, C. Morin, D. Gloria, S. Jouan, R. Pantel, M. Laurens, and A. Monroy, “A high performance low complexity SiGe HBT for BiCMOS integration,” in Proc. 1998 BCTM, 1998, pp. 93–96.
[2.25] J. Plouchart, H. Ainspan, and M. Soyuer, “A 5.2 GHz 3.3V I/Q SiGe RF transceiver,” in Custom IC Conf., 1999, pp. 217–220.
[2.26] R. Johnson, M. Zierak, K. Outama, T. Bahn, A. Joseph, C. Cordero, J. Malinowski, K. Bard, T. Weeks, R. Milliken, T. Medve, G. May, W. Chong, K. Walter, S. Tempest, B. Chau, M. Boenke, M. Nelson, and D. Harame, “1.8 million transistor CMOS ASIC fabricated in a SiGe BiCMOS technology,” in IEDM Tech. Dig., 1998, pp. 217–220.
[2.27] R. Groves, J. Malinowski, R. Volant, and D. Jadus, “High Q inductors in a SiGe BiCMOS process utilizing a thick metal process add-on module,” in Proc. 1999 BCTM, 1999, pp. 149–152.
[2.28] Mike Golio, The RF and microwave handbook. Boca Raton: CRC Press LLC, 2001.
[2.29] IEEE Std. 802.11a-1999, Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, High-speed physical layer in the 5GHz band 1999.
[2.30] Kaveh Pahlavan and Allen H. Levesque, “Wireless Information Network”, John Wiley & Sons, New York, 1995.
[2.31] Alex W. Lam and Sawasd Tantarata, “Theory and Applications of Spread Spectrum System”, Piscataway, NJ 08855-1331, May 1994.
[2.32] Richard van Nee and Ramjee Prasad, “OFDM for Wireless Multimedia Communcations”, Artech House, Boston, 2000.
[2.33] R. van Nee and R. Prasad, OFDM for Wireless Multimedia Communications, Artech House, 2000.
[2.34] John Terry and Juha Heiskala, OFDM Wireless LANs: A Theoretical and Practical Guide, Sams, 2002.
[2.35] J.J. van de Beek, M. Sandell and P.O. Borjesson, “ML estimation of time and frequency offset in OFDM systems”, IEEE Trans. Signal Processing, Volume: 45 Issue: 7, pp. 1800 -1805, Jul. 1997
[2.36] M. Speth, D. Daecke, and H. Meyr, “Minimum overhead burst synchronization for OFDM based broadband transmission”, GLOBECOM 98. The Bridge to Global Integration. IEEE, pp. 2777 -2782 vol.5, 1998
[2.37] R. Van Nee and R. Prasad, OFDM Wireless Multimedia Communications, Artech House, Boston, 2000.
[2.38] David M. Polar, Microwave and RF Wireless Systems. New York: John Wiley, 2001.
[2.39] Guillermo Gonzales, Microwave transistor amplifiers analysis and design (2nd ed.). New Jersey: Prentice Hall, 1997.
[2.40] Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.
[2.41] R. Ludwig, P. Bretchko, 2000, RF Circuit Design - theory and applications, New Jersey, USA, Prentice Hall.
[2.42] W. Alan Davis, and Krishna Agarwal, Radio Frequency Circuit Design. New York: John Wiley, 2001.
[2.43] E. A. Wolff, R. Kaul, 1988, Microwave Engineering and System Applications, USA, John Wiley & Sons.

[3.1] Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, 1998.
[3.2] S. Zhang, G. Niu, J. D. Cressler, A. J. Joseph, G. Freeman, and D. L. Harame, “The Effects of Geometrical Scaling on the Frequency Response and Noise Performance of SiGe HBTs,” IEEE Trans. Electron Devices, vol. 49 Issue: 3, pp.429–435, 2002.
[3.3] S. P. Voinigescu, M. C. Maliepaard, J. L. Showell, G. E. Babcock, D. Marchesan, M. Schroter, P. Schvan, and D. L. Harame, “A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design,” IEEE J. Solid-State Circuits, vol. 32, pp. 1430–1438, Sept. 1997.
[3.4] H. Fukui, “The noise performance of microwave transistors,” IEEE Trans. Electron Devices, vol. ED-13, pp. 329–341, Mar. 1966.
[3.5] L. Escotte, J. Roux, R. Plana, J. Graffeuil, and A. Gruhle, “Noise modeling of microwave heterojunction bipolar transistors,” IEEE Trans. Electron Devices, vol. 42, pp. 883–888, May 1995.
[3.6] G. Niu, J. D. Cressler, S. Zhang, A. Joseph, and D. L. Harame, “Noise-Gain Tradeoff in SiGe HBTs,” Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems Digest of Papers, pp.187–191, 2001.
[3.7] W. J. Kloosterman, J. C. J. Paasschens, and D. B. M. Klaassen, “Improved extraction of base and emitter resistance from small signal high frequency admittance measurements,” Proc. of the Bipolar Circuits and Technology Meeting, pp. 93–96, 1999.
[3.8] G. Niu, W. E. Ansley, S. Zhang, J. D. Cressler, C. S. Webster, and R. Groves, “Noise parameter optimization of UHV/CVD SiGe HBT’s for RF and microwave applications,” IEEE Trans. Electron Devices, vol. 46, pp. 1589–1598, Aug. 1999.
[3.9] O. Shana'a, I. Linscott, L. Tyler, "Frequency-scalable SiGe bipolar RF front-end design," IEEE J. Solid-State Circuits, vol. 36, pp. 888 -895, Jun. 2001
[3.10] A. Schmidt, S. Catala, "A universal dual band LNA implementation in SiGe technology for wireless applications," IEEE J. Solid-State Circuits, vol. 36, pp. 1127 -1131, Jun. 2001
[3.11] Ma Pingxi, M. Racanelli, Zheng Jie, M. Knight, "A 1.4 mA & 3 mW, SiGe90, BiFET low noise amplifier for wireless portable applications," IEEE RFIC Symp., pp. 237 -240, Jun. 2003
[3.12] Fu Tz-Heng, Chen Shin-Fu, J.-M Hsu, "A 0.35 μm SiGe BiCMOS RF front-end IC for TD-SCDMA receiver," IEEE Proc. Asia-Pacific Conf. on ASIC, pp. 315 -318, Aug. 2002
[3.13] D. Y. C. Lie, J. Kennedy, D. Livezey, B. Yang, T. Robinson, N. Sornin, T. Beukema, L. E. Larson, A. Senior, C. Saint, J. Blonski, N. Swanberg, P. Pawlowski, D. Gonya, X. Yuan, H. Zamat, "A direct-conversion W-CDMA front-end SiGe receiver chip," IEEE RFIC Symp., pp. 31 -34, Jun. 2002
[3.14] S. K. Reynolds, B. A. Floyd, T. Beukema, T. Zwick, U. Pfeiffer, H Ainspan, "A direct-conversion receiver IC for WCDMA mobile systems," IEEE J. Solid-State Circuits, vol. 38, pp. 1555 -1560, Sept. 2003
[3.15] Lee Jeiyoung, Lee Geunho, Niu Guofu, J. D. Cressler, J. H. Kim, J. C. Lee, B. Lee, N. Y. Kim, "The design of SiGe HBT LNA for IMT-2000 mobile application," IEEE MTT Symp. Dig., vol. 2, pp. 1261 -1264, Jun. 2002
[3.16] J. R. Long, M.A Copeland, S. J. Kovacic, D. S. Malhi, D. L. Harame, "RF analog and digital circuits in SiGe technology," IEEE ISSCC Dig. Tech. Papers, pp. 82 - 83, Feb. 1996
[3.17] D. Wang, K. Krishnamurthi, S. Gibson, J. Brunt, "A 2.5 GHz low noise high linearity LNA/mixer IC in SiGe BiCMOS technology," IEEE RFIC Symp. Dig. Papers, pp. 249 -252, May 2001
[3.18] K.-H. Chen, Y.-S. Lin, "The Design and Implementation of Power Amplifier, Low Noise Amplifier and Wideband Amplifier," Master thesis, National Chi-Nan University, Taiwan, 2004.
[3.19] H. Hashemi and A. Hajimiri, “Concurrent multiband low-noise amplifiers-theory, design, and applications,” IEEE Trans. Microwave Theory and Tech., vol. 50, pp. 288–301, Jan 2002.
[3.20] P.-W. Lee, H.-W. Chiu, T.-L. Hsieh, C.-H. Shen, G.-W. Huang, and S.-S. Lu, “A SiGe low noise amplifier for 2.4/5.2/5.7 GHz WLAN applications,” in IEEE ISSCC Tech. Dig., Feb. 2003, pp. 364–465.
[3.21] J. C. J. Paasschens and W. J. Kloosterman, “The Mextram transistor model, level 504,” Unclassified Report NL-UR 2000/811, Philips Nat.Lab., 2000
[3.22] H.C. deGraaff and W.J. Kloosterman, “Modelling of the collector epilayer of a bipolar transistor in the MEXTRAM model,” IEEE Trans. Electron. Devices, vol. 42, pp. 274-282, 1995.

[4.1] Scuderi, F. Carrara, and G. Palmisano, “VSWR-protected silicon bipolar power amplifier with smooth power control slope,” in IEEE ISSCC Int. Tech.Dig., vol. 1, pp. 194–522, Feb. 2004.
[4.2] F. Carrara, A. Scuderi, T. Biondi, and G. Palmisano, “A 1.8-GHz High-Efficiency 34-dBm Silicon Bipolar Power Amplifier,” IEEE Trans. Microwave Theory Tech., vol. 50, pp. 2963–2970, Dec. 2002.
[4.3] P. -D. Tseng, L. Zhang, G. -B. Gao,and M. F. Chang, “A 3-V monolithic SiGe HBT power amplifier for dual-mode (CDMA/AMPS) cellular handset applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 1338–1344, Sept. 2000.
[4.4] N. L. Wang, N. H. Sheng, W. J. Ho, M. F. Chang, G. J. Sullivan, J. A. Higgins, and P. M. Asbeck, “18 GHz high gain, high efficiency power operation of AlGaAs/GaAs HBT,” in IEEE MTT-S Int. Microwave Symp. Dig., pp. 997–1000, May 1990.
[4.5] Y. -J. Jeon, H. -W. Kim, H. -T. Kim, G. -H. Ryu, J. -Y. Choi, K. Kim, S. -E. Sung, and O. Byungdu, “A highly efficient CDMA power amplifier based on parallel amplification architecture,” IEEE Microwave and Wireless Components Letters, vol. 14, pp. 401–403, Sept. 2004.
[4.6] C. -W. Kim, N. Hayama, N. Goto, and K. Honjo, “High -linearity and small-chip AlGaAs/GaAs power HBTs for L-band personal digital cellular applications,” IEEE Electron Device Letters, vol. 18, pp. 147–149, April 1997.
[4.7] J. M. Cusak, “Automatic load-pull contour mapping for microwave power transistors,” IEEE Transactions on Microwave Theory and Techniques, pp.1146–1152, December 1974.
[4.8] Automated Tuner System User’s Manual, v.1.9, Maury Microwave Corporation, 1998.
[4.9] Computer Controlled Tuner System User’s Manual, v. 6.0, Focus Microwave Corporation, 1998.
[4.10] LP2 Automated Load-Pull System User’s Manual, ATN Microwave Corporation, 1997.
[4.11] F. Larose, F. Ghannouchi, and R. Bosisio, “A new multi-harmonic load-pull method for non-linear device characterization and modeling,” Digest of the IEEE International Microwave Symposium Digest, 443–446, June 1990.
[4.12] F. Blache, J. Nebus, P. Bouysse, and J. Villotte, “A novel computerized multi-harmonic load-pull system for the optimization of high-efficiency operating classes in power transistors,” IEEE International Microwave Symposium Digest, 1037–1040, June 1995.
[4.13] G. B. Gao, H. Morkoc, and M. C. Frank, “Heterojunction bipolar transistor design for power applications,” IEEE Trans. Electron Devices, vol. 39, no. 9, pp. 1987-1997, Sep. 1992.