由於多媒體系統所需處理的資料量愈來愈龐大，為了傳輸與儲存這些龐大的資料，壓縮技術愈顯重要且不可避免，可變長度編碼法是一種常見的無失真壓縮方法，因為其效果不錯，所以被許多視訊壓縮標準所採用。在本論文裡，提出了一個應用於MPEG-1/2/4的低成本可變長度解碼器。一般的可變長度解碼器通常需要使用一個相當龐大的字碼表來完成解碼動作，為了實現這樣龐大的表格必須使用大量的儲存容量，因此也花費了相當高的成本。
為了降低硬體成本，本論文提出一個有效的硬體實現方法。首先將表格裡的所有符號分到不同的群組，針對單一表格僅儲存最具代表性的符號及其內容，以產生儲存容量較小的表格，且關聯性高的表格也可被合併成單一表格，來進一步減少所需的儲存容量。該方法只需要使用少量的硬體儲存空間及一些簡單的硬體運算模組就可以得到與一般的可變長度解碼器相同的結果，故可大大地降低硬體實現成本。
我們所提出的低成本可變長度解碼器電路設計，其實作是使用Verilog，並採用Artisan TSMC 0.18μm標準元件庫進行合成；電路佈局完成後，其晶片面積為1310x1310μm2。模擬結果顯示，該實作可達到125MHz的工作頻率，並可在HD1080@30fps的要求下即時解碼MPEG-1/2/4的位元流。

The representation of most multimedia systems involves a vast amount of data, so it is inevitable to reduce the data rate for compression. Variable length coding (VLC) is a very popular lossless compression method and it has been used into many image and video coding standards. In the thesis, we present an area-efficient variable length decoder (VLD) for MPEG-1/2/4. Generally, the VLD design needs a large coding table to perform the decoding procedure, and it is implemented with larger storage space. Hence, its hardware cost quite high and unacceptable.
For reducing the hardware cost, we propose an efficient implementation method in this thesis. First, the highly correlated symbols are grouped into the same cluster. Then, we use the table merging approach to reduce the storage space of LUTs needed for MPEG-1/2/4. In the design, the size of a single LUT and the total number of LUTs required for MPEG-1/2/4 are both reduced efficiently. Thus our design achieves the target of low hardware cost.
The VLSI architecture of our MPEG-1/2/4 VLD was implemented by using Verilog HDL. We used Design Vision to synthesize the design with TSMC 0.18μm cell library. The layout for the design was generated with Astro. The chip area is 1310x1310μm2, and the clock rate is 125 MHz. Our VLD is fast enough to support video resolution of HD1080 at 30 fps for MPEG-1/2/4 real-time decoding.

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