簡易檢索 / 詳目顯示

研究生: 張祐銘
Chang, Yu-Ming
論文名稱: 以TCAD模擬基於奈米片結構的邏輯非揮發性記憶體
TCAD Simulation of Logic Non-Volatile Memory Based on Nanosheet Structure
指導教授: 盧達生
Lu, Darsen
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2021
畢業學年度: 109
語文別: 英文
論文頁數: 53
中文關鍵詞: 環繞式閘級製程邏輯非揮發性記憶體穿隧機制熱載子機制
外文關鍵詞: Gate all around, Logic non-volatile memory, Tunneling, Hot carrier injection
相關次數: 點閱:122下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 摘要 I Abstract II Acknowledgment III Content IV List of Table VI List of Figure VII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Research Objective 2 Chapter 2 Literature Review 3 2.1 Flash Memory 3 2.1.1 Memory Array 4 2.2 Logic Non-volatile Memory 6 2.2.1 Logic NVM Structure 6 2.2.2 Program and Erase Operation 7 2.2.3 Logic NVM vs. Flash 8 2.3 Nanosheet Structure 9 Chapter 3 Physical Mechanism and Environment Setup 11 3.1 Physical Mechanism 11 3.1.1 Tunneling 11 3.1.2 Hot Carrier Injection 14 3.2 TCAD physical model 15 3.2.1 Shockley-Read-Hall Model 15 3.2.2 Non-local Tunneling Model 16 3.2.3 Hot Carrier Injection Model 17 3.2.4 Threshold Voltage Extraction Model 20 Chapter 4 Result and Discussion 21 4.1 Simulation Logic NVM Structure 21 4.1.1 Device Operation 23 4.1.2 Simulation Confirmation 24 4.2 Initial Simulation 26 4.3 Structure Optimization 29 4.3.1 Bottom Width 30 4.3.2 Channel Length 32 4.3.3 Oxide Thickness 35 4.3.4 Dimension Optimization 38 4.3.5 Summary 41 4.4 Memory Array 41 4.4.1 NAND type 41 4.4.2 NOR type 44 Chapter 5 Conclusion and Future Work 46 5.1 Conclusion 46 5.2 Future Work 47 Answer to Thesis Defense Question 49 Reference 51

    [1] Nerissa Draeger, “FinFETs Give Way to Gate-All-Around,” Lam Research, Oct 26, 2020.[Online] Available: https://blog.lamresearch.com/finfets-give-way-to-gate-all-around/
    [2] "White Paper Samsung V-NAND Technology / White-Paper-Samsung-V-Nand-Technology.Pdf / PDF4PRO". 2018 .[Online] Available: https://pdf4pro.com/view/white-paper-samsung-v-nand-technology-c2ec0.html.
    [3] Wen-hao, ChingShih-Chen and WangChing-Sung Yang, “Logic-based multiple time programming memory cell,” U.S. Patent 8,355,282, Jun 17, 2010. Jan 15, 2013.
    [4] R. Bez and A.Pirovano, “Overview of non-volatile memory technology: markets, technologies and trends,” in “Advances in non-volatile memory and storage technology,” edit by Yoshio Nishi, Woodhead Publishing Series in Electronic and Optical Materials, Number 64, 2014
    [5] Aravindan, Avinash, Tony King-Smith, Nitin Dahad, and Pinkesh Sachdev. 2018. “Flash 101: NAND Flash Vs. NOR Flash - Embedded.Com”. Embedded.Com. Available: https://www.embedded.com/flash-101-nand-flash-vs-nor-flash/.
    [6] G. Ginami, D. Canali, D. Fattori, G. Girardi, P. Scintu, et al. “Survey on Flash technology with specific attention to the critical process parameters related to manufacturing Proceedings of the IEEE, 91 (4), p. 503,2003
    [7] “Intel Announces 144-Layer QLC NAND Flash - Says Penta-Level Cell (PLC) NAND Possible - Legit Reviews”. Legit Reviews. 2019.
    [8] Kinam Kim and Jungdal Choi, “Future Outlook of NAND Flash Technology for 40nm Node and Beyond,” 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop, pp. 9-11, 2006
    [9] She, Min. “Semiconductor flash memory scaling. University of California, “Berkeley, 2003.
    [10] Yoocheol Shin et al., “A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs,” IEEE International Electron Devices Meeting, 2005. IEDM Technical Digest., pp. 327-330, 2005
    [11] K. Ohsaki et al., “A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes,” IEEE J. Solid State Circuits, vol. 29, no. 3, pp. 311-316, Mar. 1994.
    [12] Chen, Hsin-Ming, et al. “Single polysilicon layer non-volatile memory and operating method thereof.” U.S. Patent No. 8,199,578. Jun 12, 2012.
    [13] S. Song, K. Chun and C. H. Kim, “A logic-compatible embedded flash memory for zero-standby power system-on-chips featuring a multistory high voltage switch and a selective refresh scheme,” IEEE J. Solid-State Circuits, vol. 48, no. 5, pp. 1302-1314, May 2013.
    [14] C. Li, J. Li, J. Shang, W. Li and S. Xu, “Multitime Programmable Memory Cell With Improved MOS Capacitor in Standard CMOS Process,” in IEEE Transactions on Electron Devices, vol. 62, no. 8, pp. 2517-2523, Aug. 2015
    [15] S. Song, J. Kim and C. H. Kim, “A Comparative Study of Single-Poly Embedded Flash Memory Disturbance, Program/Erase Speed, Endurance, and Retention Characteristic,” in IEEE Transactions on Electron Devices, vol. 61, no. 11, pp. 3737-3743, Nov. 2014
    [16] Kim, M., et al. “A 68 parallel row access neuromorphic core with 22K multi-level synapses based on logic-compatible embedded flash memory technology.” 2018 IEEE International Electron Devices Meeting (IEDM). IEEE. p. 15.4. 1-15.4. 4,2018
    [17] M. Kim, M. Liu, L. Everson, G. Park, Y. Jeon, S. Kim, et al., “A 3D NAND Flash ready 8-Bit convolutional neural network core demonstrated in a standard logic process”, IEEE International Electron Devices Meeting (IEDM), pp. 38.3.1-38.3.4, 2019.
    [18] Ye, P., T. Ernest, and M. V. Khare. “The nanosheet transistor is the next (and maybe last) step in Moore’s law.” IEEE Spectrum,2019. [Online] Available: https://spectrum.ieee.org/semiconductors/devices/the-nanosheet-transistor-is-the-next-and-maybe-last-step-in-moores-law.
    [19] S.-W. Chang et al., “First demonstration of CMOS inverter and 6T-SRAM based on GAA CFETs structure for 3D-IC applications”, IEDM Tech. Dig., pp. 254-257, Dec. 2019.
    [20] P. -J. Sung et al., “Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters,” in IEEE Transactions on Electron Devices, vol. 67, no. 9, pp. 3504-3509, Sept. 2020
    [21] Lim, Ee Wah, and Razali Ismail. “Conduction mechanism of valence change resistive switching memory: a survey.” Electronics 4.3 : 586-613,2015
    [22] Tiggelman, M. P. J. “Low series resistance structures for gate dielectrics with a high leakage current.” MS thesis. University of Twente, 2005.
    [23] C.M. Hu, S. Tam, F. Hsu, P. Ko, T. Chan, K. Terrill, “Hot-electron-induced MOSFET degradation – model, monitor and improvement, “IEEE Trans Electron Dev, 32 (2), pp. 375-385,1985
    [24] C. Fiegna, F. Venturi, M. Melanotte, E. Sangiorgi and B. Ricco, “Simple and efficient modeling of EPROM writing,” in IEEE Transactions on Electron Devices, vol. 38, no. 3, pp. 603-610, March 1991,
    [25] P. Cappelletti et al., “Flash Memories” in, Kluwer Academic Publishers, 1999.
    [26] Goudon, Thierry, Vera Miljanovic, and Christian Schmeiser. “On the Shockley-Read-Hall Model: Generation-Recombination in Semiconductors.” SIAM Journal on Applied Mathematics 67, no. 4: 1183-201,2007
    [27] “Sentaurus™ Device User Guide” Version Q-2019.12, December 2019, Synopsys, Inc.
    [28] A. Zaka, Q. Rafhay, M. Iellina, P. Palestri, R. Clerc, D. Rideau, D. Garetto, E. Dornel, J. Singer, G. Pananakakis, C. Tavernier, and H. Jaouen, “On the accuracy of current TCAD hot carrier injection models in nanoscale devices,” Solid-State Electronics, Aug 2010.
    [29] JOSEPH, Thomas. “Theoretical Study of Short Channel Effects in Planar Bulk nMOS.” Chemnitz: Technische Universität Chemnitz , 2016.
    [30] Tomiye, Hideto, et al. “A novel 2-bit/cell MONOS memory device with a wrapped-control-gate structure that applies source-side hot-electron injection.” 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No. 01CH37303). IEEE, 2002.
    [31] D. H. Li”, W. Kim, J. H. Lee and B. -G. Park, “Thickness-dependence of oxide-nitride-oxide erase property in SONOS flash memory,” 2009 International Semiconductor Device Research Symposium, pp. 1-2,2009

    無法下載圖示 校內:2026-08-20公開
    校外:2026-08-20公開
    電子論文尚未授權公開,紙本請查館藏目錄
    QR CODE