不管是語音或影像，經常會因為受到不同的因素導致雜訊出現，中值濾波器可以達到去除雜訊的效果，常被應用在語音訊號跟影像處理上，在多種不一樣的去除雜訊濾波器中是一個很重要的角色。
在本篇論文中，採用低功率部分位元級(bit-level)的一維中值濾波器架構。一般而言，不同的影像或語音標準需要不同的固定資料輸入量(window-size)和資料位元寬度(bit-width)的中值濾波器，導致需要編寫多個不同資料輸入量(window-size)和資料位元寬度(bit-width)的中值濾波器。在本文中，提供Soft-IP彈性地產生中值濾波器，此新的硬體架構可以同時支援不同資料輸入量(window-size)和資料位元寬度(bit-width)。換句話說，經過參數設定，可以決定讓此中值濾波器彈性的對應各種不同資料量(window-size)和位元寬度(bit-width)。
本論文中，所有架構都是由Verilog HDL實現，並由Synopsys Design Compiler使用TSMC 90nm的標準元件庫做合成。實驗結果顯示，此新架構可以根據不同資料輸入量(window-size)和資料位元寬度(bit-width)，彈性變更中值濾波器的電物設計，並且有效的減少功率消耗。

Median filter is often used in audio processing or image processing. No matter in audio or image processing, noise is inevitable due to many factors. In order to remove noise, median filter plays an important role in many different removing noise filters.
In this dissertation, we propose a low-power architecture of partial-bit-level and one-dimensional median filter. In principle, distinct audio or image standards need different fixed data window-size and bit-width, resulting in a need for the compilation of multiple hardware architecture of median filter which corresponds with different data window-size and bit-width. The new Soft-IP proposed in this dissertation can support different data window-size and bit-width simultaneously. In other words, after setting parameters, this median filter architecture is able to correspond to a variety of the combination of data window-size and bit-width.
The proposed design was implemented by using Verilog HDL and synthesized by Synopsys Design Compiler with TSMC 90nm library. The experimental results demonstrated can reduce power consumption and flexibility change different window-size and bit-width of median filter.

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