本論文研製整合GIPD天線之CMOS 60-GHz功率放大器、V-band堆疊式功率放大器及整合W-band收發開關之 94-GHz寬頻放大器，皆採用TSMC 90-nm GUTM CMOS製程進行設計。論文第一部分為功率放大器簡介，概述功率放大器各項效能參數並介紹各種架構。論文第二部分為整合GIPD天線之CMOS 60-GHz功率放大器晶片設計，此設計採用四路變壓器功率結合，藉由差動輸出減輕毫米波頻段變壓器功率結合器所面臨之各輸入埠阻抗不平衡問題，以降低結合器損耗，輸出則藉覆晶技術(flip chip)由金凸塊(gold bump)異質整合一高效率GIPD on-chip雙埠韋瓦第天線，利用差動天線來完成終端空間功率結合，整體結合器損耗有不錯之表現。論文第三部分為V-band堆疊式功率放大器，該放大器利用電晶體堆疊來提升輸出功率， 在不使用功率結合器之情況下成功提升輸出功率，因此也擁有小面積優勢。論文第四部分為W-band寬頻功率放大器，設計上採用串接五級疊接(cascode)架構並搭配A類放大器之偏壓形式實現，同時藉由增益提升技巧(gain boosting)的方式使其具有較佳功率增益來減輕其它發射機前端電路的設計負擔，並利用各級級間匹配控制增益分佈，使其整體3-dB增益頻寬達到20%，且在其頻寬內，輸入及輸出返回損耗皆大於10-dB。電路設計以Agilent ADS與全波電磁模擬軟體進行模擬，量測部份皆是採用on-wafer方式進行，根據欲量測參數特性之不同，相關量測架設方式亦有所調整。

This thesis presents the design of millimeter-wave (MMW) RF active antenna as well as MMW V- and W-band power amplifiers. In the 60 GHz active antenna, the heterogeneous integration technique implemented by standard TSMC 90-nm GUTM CMOS process and ASFC GIPD process is adopted for addressing the low radiation efficiency issue of on-chip CMOS antenna. It utilizes flip-chip technique with gold bump to integrate the different processes. For enhancing equivalent isotropically radiated power (EIRP), 4-way combining power amplifier is designed by using distributed active transformer as combiner. In order to improving power added efficiency (PAE) of the PA, differential output is adopted to mitigate the input port mismatched of DAT in MMW band, and it uses differential input GIPD antenna to achieve final space combining to avoid use of additional balun. In a 60 GHz CMOS power amplifier design, the stacked structure with using inter-node matching network is employed. For chip size ctrtria, the adopted stacked structure can improve the output power without using large size output combiner. The power gain and power added efficiency performance is significantly improved by inter-node matching technique. In the design of a W-band CMOS power amplifier, a five stage common-source (CS) cascade structure with gain-boosting technique is adopted for power gain, 3-dB gain bandwidth, and gain flatness criteria. In order to achieve 20% bandwidth and enough gain flatness, it arranges the gain to frequency distribution of each stage by inter-stage matching network. The measured performances of the designed MMW RFICs are all performed by using the on-wafer measurement. Simulation and measurement results are compared and discussed.

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