隨著技術的進步，微系統的微縮變得越來越重要。為了解決在內連線結構中電阻-電容延遲的問題，因此發展出銅或銅合金導線製程，但也衍生出其他問題。由於導線與介電層間材料性質之差異，使得內連線結構在製程中升溫、降溫過程常引發應力集中的問題，高應力可能會造成界面脫層、裂紋或是誘發孔洞現象，降低元件的可靠度。另外，異質材料間之界面接合強度也是影響內連線結構可靠度的重要因素。因此，內連線結構之可靠度是一重大關鍵，若能預測應力分布以及破壞行為，將可為製程設計提供相當重要的資訊。
本論文將利用現行的商用有限元素分析軟體ANSYS來進行模擬分析。建立內連線結構受熱模型，進行整體的應力場分析。藉此得到製程溫度、幾何參數以及低介電常數材料性質對內連線結構之影響。接著藉由應力場的分佈，評估局部區域的模型，引進雙材料界面破壞力學之觀念，以數值模擬判斷發生脫層破壞之可能性。最後，以最小化應力值為目標，更改內連線結構的幾何參數，最佳化層內連線的結構。
從研究結果發現，因材料彼此之間熱膨脹係數及彈性模數的不匹配，對在升/降溫過程中產生之殘留應力有顯著的影響。結果顯示低介電常數材料與金屬導線的熱膨脹不匹配和金屬導線之間距是影響應力分布的重要因素，且內連線結構應力亦會隨著低介電常數材料之楊氏模數的降低或熱膨脹係數的提高而上升，使得裂紋開裂現象的機率大大提高，降低元件的可靠度。故在設計內連線結構時，可以選用較高楊氏模數與熱膨脹係數較低的材料作為介電層，以提高元件的可靠度。另外，較低的製程溫度也對改善可靠度有正面的影響。以上結果可以提供開發者作為設計的參考依據，以達最佳化的設計之目的，並縮短開發之時間。

With the development of technology, scaling of microsystem has become more and more important. In manufacturing processing, using copper wire for connecting each micro-device and constructing logical circuit to reduce R-C time delay is a major technique. However, during fabrication, the thermo-mechanical mismatch between materials generates high stresses, which cause the generation of stress-induce voiding, cracks, and interface delaminations. These defects strongly affect the reliability of integrated circuit devices. In addition, the interfacial bonding strength between bi-materials also plays a significant role in reliability of microsystem. As a result, the reliability of interconnect structures becomes one major concern of modern microelectronics.
This thesis utilizes mechanics of materials, fracture mechanics, and finite element method to analyze cracking and interfacial delamination of thin films and interconnect structures, as well as for evaluating that the stress and energy release rate within the structures under cyclic thermal loadings. Parametric studies for investigating the sensitivity of each physical parameter like temperature, geometry parameters and properties of low-k materials on the stress generation, strain energy release rate, and crack growth are presented. Finally, optimize size parameters of the interconnect structure to minimize stresses.
The results show that thermal mismatch between different materials and spaces on wires are significant factors for generating high stresses. It is also found that selecting the low-k materials with higher Young's modulus and lower coefficient of thermal expansion could avoid causing high stress. Lower processing temperature could improve the reliability of interconnect structures, and smaller energy release rate could prevent interfacial delamination of thin films. The study results should be useful for providing engineers the conceptual design access of interconnect structures, and to reduce development time.

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