本研究透過神經網路模型壓縮與 FPGA 硬體加速設計，建立一套低功耗即時行人偵測系統。模型壓縮方面，使用 YOLOv3 Tiny 作為基準模型進行架構壓縮，並且將標準卷積替換為深度可分離卷積。隨後使用通道層級知識蒸餾技術提升壓縮後模型的特徵表達能力與準確度。接續採用結構化迭代剪枝移除逐點卷積中的冗餘濾波器，大幅減少推論計算負擔與硬體乘法器及記憶體資源消耗。最後透過訓練後量化將模型量化至 8 位元整數格式，進一步縮減硬體儲存需求。FPGA 硬體加速設計方面，使用管線串流與資源複用的複合式硬體架構，在有限的硬體資源與推論速度之間取得良好平衡。實驗結果顯示，YOLOv3 Tiny 經本研究之模型壓縮流程後，參數量與計算量分別縮減 99.00% 及 97.34%，mAP@50 僅下降 5.05%。結合本研究所提出之硬體架構，於約十萬個邏輯閘等級的 FPGA 開發板上，在 50 MHz的工作時脈下，僅需 13.18 毫秒的低延遲即可完成行人偵測。

This study integrates neural network model compression and FPGA hardware acceleration to develop a low-power, real-time pedestrian detection system. YOLOv3 Tiny is adopted as the baseline model and compressed through architectural simplification, depthwise separable convolutions, channel-wise knowledge distillation, structured iterative pruning, and 8-bit post-training quantization. These techniques significantly reduce the model size and computational complexity while maintaining satisfactory detection performance. For hardware acceleration, a hybrid architecture combining pipeline streaming and resource reuse is designed to balance FPGA resource utilization and inference speed. Experimental results show that the proposed compression process reduces the number of parameters and computational complexity by 99.00% and 97.34%, respectively, while the mAP@50 decreases by only 5.05 percentage points. The proposed system achieves an inference latency of approximately 13.18 milliseconds per image on the Altera DE2-115 FPGA at an operating frequency of 50 MHz, demonstrating its feasibility for real-time embedded pedestrian detection.

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