近年來半導體元件趨於微型化，製程技術之精密度不斷提升，在高積集度以及線寬微小化的要求下，內連線所產生之R-C time delay越來越嚴重，因此發展出銅製程。雖然銅製程改善了R-C time delay之問題，但其所採用之低介電常數材料，大多屬於低楊氏係數、高熱膨膨脹係數之多孔性材料，由於低介電材料與銅之間熱膨脹係數之mismatch以及材料性質之差異，使得結構在製程惡劣的環境中，引發應力集中等問題。由於應力過高所導致的void、cracking等缺陷，會影響整體元件之基本電子特性，降低可靠度，因此應力的預測，於製程設計是一項重要的資訊。我們希望於設計過程中，設計出內連線結構之應力達到最小之程度，然而實際上，從Layout開始直到最後產品的完成，中間必須經過多道步驟，因此設計者無法在設計的同時得到製程後之結果，對於設計之改善需要耗費大量時間。本文所討論之問題，在於如何建立一套有系統之分析方式，以提高分析設計之效率。我們以電腦輔助設計之方式，利用本研究室所發展之Z-Fab軟體建構出虛擬內連線結構，其中包含了金屬層、介電層、蝕刻中止層及阻障層。此虛擬內連線結構並可提供給後續有限元素法軟體做應力與破壞之分析，找出相關參數對於結構應力之影響；另外發展一內連線受熱之力學模型，並與FEM模擬做驗證，可利用此模型，針對不同幾何參數與溫度變化，初步對於結構內部之應力做快速估計。我們希望藉由此一有系統之分析方法，提供開發者設計的方針，達成設計最佳化的目的，並縮短開發之時間。

With the rapid growth in semiconductor industry and the advancing in fabrication technology, the minimum feature size is continuously deceasing; this causes intrinsic capacitance and resistance of interconnects which leads to transportation delay, an important concern in integrated circuit (IC) devices. In order to reduce this transportation time delay in interconnects; novel interconnection method such as copper process is now widely applied. However, due to the mismatch in thermal mechanical properties between low dielectric constant (low-k) materials and coppers, during fabrication process, creates enormous stress which causes the generation of stress-induced voiding or cracking ; they are becoming significant failure mechanisms. These defects affect the reliability of integrated circuit devices. As a result, it is important to predict the stress distribution in interconnect structures and to analyze the influence factors within. However, the designers cannot acquire the stress information during the IC development; trial and errors and case by case studies are time consuming. In this thesis, a concept of systematic analysis method in the purpose of improving analysis efficiency is proposed. By using the Z-Fab utility developed in our lab to build up the virtual interconnect structures and subsequently to provide finite element analysis (FEA) for performing parameters studies. In addition, a mechanics model of interconnect structures had been developed. The model could preliminary estimate stresses rapidly with different geometry and temperature parameters. Using this systematic analysis method, it is possible to provide designers the conceptual design of interconnect structures, and to reduce the development time.

[1] Tummala, ”Fundamentals of Microsystems Packaging”,p.8, 2001
[2] The International Technology Roadmap for Semiconductor, 2004
[3] P.J Wolf, et al, “ Overview of Dual Damascene CuLow-k Interconnect.”
[4] P. A. Flinn, et al, “Stress-induced void formation in metal lines”, MRS Bulletin, Vol. 18, No. 12, 1993
[5] E. T. Ogawa, et al, “Electromigration Reliability Issues in
Dual-Damascene Cu Interconnections”, IEEE Transactions on Reliability, Vol.51, No.4, 2002
[6] J. M. Paik, et al.,”Effect of low-k dielectric on stress and stress-induced damage in Cu interconnects ” Microelectronic Engineering,Vol.71,2004
[7] Y.-L. Shen, et al, “Modeling of Thermal Stresses in Metal Interconnects Effects of Line Aspect Ratio”, Journal of Applied Physics, Vol.82, No.4, 1997.
[8] C.C. Lee, et al., ”Stability of J-integral Calculation in the Crack”, IEEE, 2006.
[9] 莊達人編著，VLSI 製造技術，高立圖書有限公司，第二版，2002年。
[10] M..Bohr, “Interconnect Scaling- The Real Limiter to High Performance ULSI”, IEEE IEDM Proc., 241 (1995).
[11] P. Josh Wolf ERC, Retreat Stanford：New Chemistries & Tools for
scCO2 Processing of Thin Films, 2003.
[12] SEMulator3D: http://www.coventor.com/3dsemi.html
[13] 葉修銘，以幾何模擬法分析微機電製程與建立其電腦輔助設計模組，國立成功大學機械系碩士論文，2004。

[14] G. Koppelman, ”OYSTER, A Three-Dimensional Structural Simulator for Microelectromechanical Design,” Sensors and Actautors, Vol. 20, PP.179-185,1989.
[15] S. D. Senturia, R. M. Harris, B. P. Johnson, S. Kim, K. Nabors, M. A. Shulman, and J. k. White, “A computer-aided design system for microelectromecnanical systems (MEMCAD),” J. Microelectromech. Syst., Vol. 1,No. 1,March 1992.
[16] M.T. Bohr, “Intel's 90 nm technology: Moore's law and more”, in: Intel Developer Forum, Fall 2002.
[17] M. H. Sadd, Elasticity Theory, Applications, and Numerics, Wiley, 2005.
[18] S. P. Timoshnko, and J. N. Goodier, Theory of Elasticity,Central,1986.
[19] J.-H. Zhao, et al., “Simultaneous measurement of Young's modulus, poisson ratio, and coefficient of thermal expansion of thin films on substrates”, Journal of Applied Physics, Vol. 87, No.3, 2000
[20] J.-H. Zhao, et al., ” Thermomechanical property of diffusion barrier layer and its effect on the stress characteristics of copper submicron interconnect structures” Microelectronics Reliability, Vol. 42, No. 1, January, 2002.
[21] E. T. Ogawa, et al, “Stress-induced voiding under vias connected to wide Cu metal leads”, 40th Annual lnternational Reliability Physics Symposium, 2002
[22] Mari ABE, et al, “Effect of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voidinig(SIV) in Cu Dual-Damascene Interconnects”, Japanese Journal of Applied Physics, Vol. 44, No. 4B, 2005
[23] K. Maexa, M. R. Baklanov, “Low Dielectric Constant Materials for Microelectronics”,Journal of Applied Physics, Vol. 93, No.11, 2003
[24] Jeff Snodgrass, et. al, “Adhesion and Mechanical Reliability of Low-k Interconnect Structures”, Department of Materials Science and EngineeringStanford University.
[25] T.L.Anderson, Fracture Mechanics,CRC,1995
[26] Cornell Fracture Group http://www.cfg.cornell.edu/index.htm