| 研究生: |
陳若元 Chen, Jo-Yuan |
|---|---|
| 論文名稱: |
MPEG-4即時視訊編解碼器於系統晶片之實現 Real-Time MPEG-4 Codec System Based on SoC Realization |
| 指導教授: |
楊家輝
Yang, Jar-Ferr |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2006 |
| 畢業學年度: | 94 |
| 語文別: | 中文 |
| 論文頁數: | 109 |
| 中文關鍵詞: | 系統晶片 、嵌入式系統 、視訊編解碼 |
| 外文關鍵詞: | DM320, SoC, MPEG-4, Video Codec, Real-Time |
| 相關次數: | 點閱:83 下載:3 |
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MPEG-4 即時視訊編解碼器於系統晶片之實現
陳若元* 楊家輝**
國立成功大學 電腦與通信工程研究所 通訊與網路組
摘要
本論文的主要研究是利用德州儀器公司出產之TMS320DM320
系統單晶片,實作出適合於嵌入式系統下之MPEG-4 即時編解碼系
統。在DSP 端實現本系統必須克服嚴格記憶體限制、平行處理及加
速指令效率等問題。首先,改寫關鍵程式或演算法,使程式上的運
算適用於單晶片中的硬體加速模組以增進系統運算效能,接著對執
行頻繁的程式部分進行組語改寫,最後利用硬體加速器及DSP 系統
相互之間的獨立性,進行平行處理,以達到即時編解碼的效能。實
驗結果顯示MPEG-4 解碼系統可在VGA 格式即時解碼,而編碼系
統可達到CIF 格式即時編碼錄影的效能。
另一方面,我們也以MPEG-4 解碼器為例,在不影響解碼器統
效能的情況下,將疊置與動態載入的技術,運用到嵌入式系統上以
提升內部記憶體的使用效率,達到節省記憶體空間的目的。
*作者 **指導教授
Real-Time MPEG-4 Codec System
Based on SoC Realization
Jo-Yuan Chen * and Jar-Ferr Yang**
Institute of Computer and Communication Engineering,
National Chen Kung University
1 University Road, Tainan, Taiwan, R.O.C.
ABSTRACT
In this thesis, we design a real-time MPEG-4 video codec system based
on System-on-a-Chip - TMS320DM320 manufactured by Texas Instrument
(TI) Incorporation. While implementing our system on DSP unit, we must
consider solving the problems regarding to memory limitation, system
parallelization and efficiency usage of fast instruction sets, etc. Firstly, we
correct the major part of the codes or algorithms, and these operations on the
program will be processed in efficient way by calling hardware acceleration
module. Then, we translate the frequently-used C codes into assembly codes.
Finally, according to the independency between hardware acceleration
module and DSP system, we arrange system parallelization in order to
accomplish a real-time MPEG-4 codec. Experiments show that our
implementation can achieve real-time decoding and encoding in VGA and
CIF format, respectively.
In addition, take MPEG-4 decoder for example; we improve the
efficiency of memory management by using overlay and dynamic linking
loader technique without the influence of decoding performance.
*The Author **The Advisor
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[3] ISO/IEC 14496-2:2003, “Coding of Audio-Visual Objects - Part 2:
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1-55-860496-0.
[9] 陳文欽, 游燦營, “Design of an Embedded Dynamic Linking Loader
And Its Application to RSA Algorithm”, 2004.
[10] 莊俊傑, “Design and Implementation of Limited Memory Management
in Heterogeneous Embedded System”, 2006.
[11] TMS320C54x DM Chip Support Library, Texas Instruments, 2003.
[12] TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals,
Texas Instruments, 2001.
[13] TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction
Set,Texas Instruments, 2001.
[14] TMS320C54x DSP Reference Set, Volume 3: Algebraic Instruction Set,
Texas Instruments, 2001.
[15] TMS320DM320 CPU and Peripherals, Technical Reference Manual
Version 1.5
[16] TMS320DM320 iMX API Library, Version 0.43
[17] Programming the DM320 Sequencer, Texas Instruments, 2004.
[18] Code Composer Studio User’s Guide, Texas Instruments, 2000.
[19] Microsoft Extensible Firmware Initiative FAT32 File System
Specification, FAT: General Overview of On-Disk Format Version1.03,
December 6, 2000 Microsoft Corporation