近年來，隨著視訊多媒體的蓬勃發展與通訊技術的進步，各種包含語音、影像與圖片之多媒體通訊應用皆不斷推陳出新。而許多消費性電子產品都加入了顯示照片或影片的功能。然而，影像通常會在取得的過程或是傳送的階段受到雜訊的污染，而造成了影像視覺品質的降低，所以去除雜訊的技術是影像處理上非常重要的一個議題。對於許多需要滿足即時處理的嵌入式應用產品來說，去雜訊技術的硬體實作是不可或缺的；然而對消費者來說，當他們在選擇消費性電子產品時，價格往往是最重要的考量。因此，在本論文中，我們希望能研發出一個低成本的去雜訊技術之硬體實作。
此外，影像縮放技術亦是多媒體通訊應用中一項十分重要的課題，它已經廣泛的被使用於許多的應用，比如：高畫質數位電視，液晶電視，數位錄放影機，影印機，醫學影像等等。當要顯示的影像解析度不同於目的設備所設定的解析度大小時，就需要使用到影像縮放技術。舉例來說，當我們需要在高畫質電視裡顯示解析度較小的影像時就需要將影像放大到符合該裝置的解析度，而如果需要在小尺寸可攜式液晶顯示器裡顯示較高畫質的影像，就需要將該影像縮小。在許多實際的即時顯示設備中，影像縮放技術一般都加在使用者端的設備中，也因此，一個簡單且適合以低成本VLSI硬體實作的影像縮放技術是非常必要的。本論文即針對此應用於多媒體顯示的兩大領域進行探討。
針對影像去雜訊技術，在本論文中我們提出了一個能保留影像邊緣特性的雜訊移除演算法(SEPD)及其硬體實作，來移除fixed-valued脈衝雜訊。這個方法的計算複雜度很低，而且它所需的記憶體緩衝區只有兩列影像大小的寬度，所以整個的硬體成本極低。此方法會先以一個小的工作視窗來偵測此像素是否為雜訊點，並找尋此工作視窗中存在的邊緣方向，最後利用所偵測出的邊緣線來預估此像素的重建值。若此像素被偵測為雜訊點，則以此重建值取代它。所以SEPD可以有效的保留影像邊緣特性。實驗結果顯示我們的方法不論在主客觀數據上都比現行的方法來的好。此外，我們也提出了這個設計的管線化VLSI架構，根據SYNOPSYS的Design Vision和TSMC’s 0.18μm的標準元件庫合成結果，此電路每秒處理量可以達到167百萬像素/秒的速度。
在影像縮放技術方面，我們提出一個參考影像邊緣的面積像素影像縮放演算法及其硬體實作。我們定義了一個改良的 area-pixel 模型，這個模型採用整數的參數作為運算，且藉由捕捉來源影像局部特徵的特性，更精準的估算出目標像素值。實驗的結果也顯示，此方法可以有效的保留住影像的邊緣特徵，而且在影像品質及數據比較上都比傳統的方法有更好的表現。因為我們的方法只需要低複雜度的運算且運算極有規律，因此非常適合VLSI硬體的實作。針對此，我們提出了一個高效能的七級管線化的硬體架構。根據SYNOPSYS的Design Vision和TSMC’s 0.18μm的標準元件庫合成結果，此電路所需的邏輯閘數目為10.4K，且運作速度可以到達 200 MHz 。

The fundamental characteristics of multimedia system are that they incorporate continuous media such as voice, full-motion video, and graphics. Many electronic devices need the display technique to show photos and/or videos. However, images are often corrupted by impulse noise during image acquisition and transmission. Thus, the denoising technique becomes a very important issue in image preprocessing. For real-time embedded applications, the VLSI implementation of denoising process is necessary and should be considered. For customers, cost is usually the most important issue while choosing consumer electronic products. Therefore, we hope to focus on low-cost denoising implementation in this dissertation.
Furthermore, the scaling algorithm is a very important subject in image processing. It has been used in many applications such as HDTV, LCD-TVs, digital video camcorders, copy-print machines, medical imaging and so on. It is indispensable when the resolution of an image generated by a source device is different from the screen resolution of a target display. For example, we have to enlarge images to fit HDTV or to scale them down to fit the mini-size portable LCD panel. In many practical real-time applications, the scaling process is included in end-user equipment, so a good lower-complexity scaling technique, which is simple and suitable for low-cost VLSI implementation, is needed. In this dissertation, we focus on these two topics for display.
On the denoising topic, we propose a simple edge-preserved denoising technique (SEPD) and its VLSI implementation for removing fixed-valued impulse noise. The design requires only low computational complexity and two line memory buffers. Its hardware cost is quite low. SEPD can preserve the edge features efficiently by finding a directional edge existed in the window centered on the current pixel and using the edge to determine the reconstructed value of current pixel. Extensive experimental results demonstrate that our method can obtain better performances in terms of both subjective and objective evaluations than those state-of-the-art impulse denoising techniques. The VLSI architectures of the proposed design were implemented by using Verilog HDL. We used SYNOPSYS Design Vision to synthesize the designs with TSMC’s 0.18μm cell library. Synthesis results show that the proposed design yields a processing rate of about 167 M samples/second.
On the scaling topic, we present an edge-oriented area-pixel scaling processor. We define a modified area-pixel model with only fixed-point coefficients and implement it with the proper and low-cost VLSI circuit. A simple edge catching technique is adopted to preserve the image edge features effectively so as to achieve better image quality. Compared with the previous low-complexity techniques, our method performs better in terms of both quantitative evaluation and visual quality. The seven-stage VLSI architecture for the proposed design was implemented and synthesized by using Verilog HDL and Synopsys Design Compiler, respectively. In our simulation, the circuit can achieve 200 MHz with 10.4K gate counts by using TSMC 0.18μm technology.

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