| 研究生: |
劉諭勳 LIOU, YU-SYUN |
|---|---|
| 論文名稱: |
應用陰影疊紋法量測電子元件的翹曲量及系統升溫校正 Measurement of Warpage of Electronic Components and System Calibration under Heating Condition Using Shadow Moire Method |
| 指導教授: |
陳元方
Chen, Yuan-Fang |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 機械工程學系 Department of Mechanical Engineering |
| 論文出版年: | 2016 |
| 畢業學年度: | 104 |
| 語文別: | 中文 |
| 論文頁數: | 106 |
| 中文關鍵詞: | 陰影疊紋法 、翹曲量 、雙立方樣條內插 |
| 外文關鍵詞: | Shadow Moiré, Warpage, Bicubic Spline Interpolation |
| 相關次數: | 點閱:111 下載:0 |
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陰影疊紋系統現今最常應用於量測電子元件的翹曲量,在高溫量測時由於系統會因為加熱膨脹產生不可預期的變動,最後造成量測上的誤差。
本文主要目的是應用陰影疊紋法系統,在高溫狀態下檢測電子元件翹曲量變化。首先依據JEDEC標準提出以最小平方法(Least Mean Squares)法初步將晶片旋轉至水平,運用組合法將高於底座平面的點再進行組合判別,最後可得最高底座平面。且以模擬馬鞍形與半圓柱形貌方式驗證搜尋法的正確性。另外以同組電子晶片將實驗所得翹曲量數據與華東科技量測數據比較差異。
在升溫量測時,利用校正片在不同溫度時,所量測到的量測值與已知值之間的誤差,當作校正值。本文使用雙立方樣條內插,將校正片上選取二十五個校正值內插出方形校正值區域。經過校正片升溫量測的結果,絕對平均誤差最大為1.51um,由此可知此方法可提高量測準確度。
Shadow moiré method is commonly used to measure warpage of electronic components. When measuring specimen by shadow moiré system under heating condition, the system will produce unpredictable changes due to thermal expansion and lead to measurement error.
In this paper, the major purpose is to measure the warpage of electronic components by using shadow moiré method under high temperature condition. According to JEDEC STANDARD, we use least mean squares to rotate the chip to be horizontal at first. Next, we discriminate the point above seating plane by combined method,so that we can get the highest seating plane. Then, we simulate the profiles of saddle and half cylinder to examine the correctness. And we will compare our measuring result to the warpage that measured by Walton Engineering Inc.
We can get error between measured value and standard value that measured by calibration plate in different temperature. The error is called calibration value. In this paper, we use bicubic spline interpolation to interpolate twenty-five calibration value of twenty-five points that we choose on calibration plate. After that, we can get a rectangular calibration area. According to the testing result, the maximum Absolute average error is 1.51um. It shows that shadow moire system calibration program under heating condition can make accuracy of measurement much higher.
1. L. J. Chiponis, S. Jose,“Coplanarity Tester Surface Mounted Device, ” United States Patent, Appl. No. 38,305, 1988.
2. T. Kida,“Means for Measuring Coplanarity of Leads on an IC Package, ” United States Patent, Appl. No.729,921, 1993.
3. S. Bilodeau,“Method for Coplanarity Inspection of Package or Substrate Warpage for Ball Grid Arrays, Column Arrays,and Similar Structures, ” United States Patent, Appl. No.253,989, 1995.
4. JEDEC STANDARD “Coplanarity Test for Surface-Mount Semicondutor,”2003.
5. JEDEC STANDARD “High Temperature Package Warpage Measurement Methodology, ”2005.
6. Y. Kwon, S. Danyluk, L. Bucciarelli and J. P. Kalejs, “Residual Stress Measurement in Silicon Sheet By Shadow Moire Interferometry, ” Journal of Crystal Growth, Vol.82, No.1-2, pp.221-227, Jul 22-25, 1986.
7. R. C. Schwarz, “Determination of Out-of-Plane Displacements And The Initiation of Buckling In Composite Structural Elements, ” Experimental Techniques, Vol.12, No.1, pp.23-28, January, 1988.
8. R. Stiteler, I. C. Ume, “In-Process Board Warpage Measurement in a Lab Scale Wave Soldering Oven, ” IEEE Transactions on Components, Packaging, And Manufacturing Technology, Part A, Vol.19, No.4, pp.562-569, December, 1996.
9. R. Stiteler, I. C. Ume, “System for Real-Time Measurement of Thermally Induced PWB/PWA Warpage, ” Journal of Electronic Packaging, Vol.119, pp.1-7, March, 1997.
10. Wang , W. C and Y. U. Liu, “Moire technique and measurement of vibrationsMeasurement of warpage of electronic packagings after machining by phase-shifting shadow moire method ” Source Proceedings of SPIE - The International Society for Optical Engineering, v 4537, pp 20-24, 2001.
11. Y.A. Moreno, “Moire technique and measurement of vibrations”Proceedings of SPIE - The International Society for Optical Engineering, v 4419, pp 202-205, 2001
12. S.P Cao., K.A. Ngoi, Y.F Song, L. Lim, “A new Moire method for industry on-line measurement” Source: Proceedings of SPIE - The International Society for Optical Engineering, v 4317, pp 186-191, 2001
13. W. Yinyan and H. Patrick, “Measurement of Thermally Induced Warpage of BGA Packages/Substrates Using Phase-Stepping Shadow Moire, ” IEEE/CPMT Electronic Packaging Technology Conference, pp.283-289, 1997.
14. W. Yinyan and H. Patrick, “On-line Measurement of Thermally Induced Warpage of BGAs with High Sensitivity Shadow Moire, ” The International Journal of Microcircuits and Electronic Packaging, Vol.23, No.2, pp.191-196, Second Quarter 1998.
15. J. Gregory , and I. Charles, “Warpage Studies of HDI Test Vehicles During Various Thermal Profiling, ” Electronic Components and Technology Conference, IEEE, pp.1640~1646, 2000.
16. Y. Polsky, W. Sutherlin, and I. Charles, “A Comparison of PWB Warpage Due to Simulated Infrared and Wave Soldering Processes, ” IEEE Transactions On Electronics Packaging Manufacturing, Vol.23, No.3, pp.191~199, July, 2000.
17. K. Verma, D. Columbus, B. Han and B. Chandran, “Real-Time Warpage Measurement of Electronic Components With Variable Sensitivity, ” Electronic Components and Technology Conference, IEEE, pp.975-980, 1998.
18. K. Verma, D. Columbus and B. Han, “Development of Real Time/Variable Sensitivity Warpage Measurement Technique and its Application to Plastic Ball Grid Array Package, ” Transactions On Electronics Packaging Manufacturing, IEEE, Vol.22, No.1, pp.63-70, January 1999.
19. 陳志松, “應用光測力學在電子構裝之量測分析, ” 國立臺灣大學應用力學研究所碩士論文, 2000.
20. 鄭仲豪, “應用相位移陰影疊紋量測高溫下晶圓的變形”,國立成功大學機械工程學系碩士論文, 2002。
21. 莊佳橙, “應用自動化相位移陰影疊紋系統量測晶圓外型”,國立成功大學機械工程研究所碩士論文, 2003。
22. 楊韶綸, “條紋反射法之向量解析與應用”,國立成功大學機械工程研究所碩士論文,2007。
23. 陳璟照, “應用陰影疊紋法量測電子元件的共面性與翹曲量”,國立成功大學機械工程研究所碩士論文,2008。
24. 林捷, “相位移陰影疊紋影像錯誤區域之自動化偵補及系統升溫校正”,國立成功大學機械工程研究所碩士論文,2013。
校內:2026-09-01公開