| 研究生: |
張又軒 Chang, Yu-Hsuan |
|---|---|
| 論文名稱: |
多層氧化鋅與氧化鎵主動層在不同濺鍍環境之薄膜電晶體結構特性研究 Study on Structural Characteristics of Thin Film Transistors of Multti Active Layer Zinc Oxide and Gallium Oxide in Different Sputtering Environment |
| 指導教授: |
賴韋志
Lai, Wei-Chih |
| 學位類別: |
碩士 Master |
| 系所名稱: |
理學院 - 光電科學與工程學系 Department of Photonics |
| 論文出版年: | 2018 |
| 畢業學年度: | 106 |
| 語文別: | 中文 |
| 論文頁數: | 111 |
| 中文關鍵詞: | 下閘極 、氧化鋅 、氧化鎵 、多層結構 、共濺鍍 、載子遷移率 、臨界電壓 、次臨界值擺幅 、介面缺陷密度 、霍爾量測。 |
| 外文關鍵詞: | Bottom gate, Zinc oxide, Gallium oxide, Multilayer, Cosputter, Carrier mobility, Threshold voltage, Subthreshold swing, Interface trap density, Hall measurement |
| 相關次數: | 點閱:83 下載:1 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
本論文主要探討空乏型不同的下閘極(bottom gate)金屬結構下,主動層(半導體層)以不同材料之成長方式成長,以實現薄膜電晶體元件開關特性,並著墨在元件閘極金屬結構不同、主動層中以磁控濺鍍機(sputter)成長氧化鎵時的不同氧氣流量、射頻(Radio frequency,RF)功率瓦數,以及元件總體快速熱退火系統(Rapis thermal annealing,RTA)的退火溫度、純氧化鋅、純氧化鎵、氧化鋅摻雜氧化鎵等三種結構操作變因之研究,並對不同閘極電壓(Vg)下之汲極電流(Id)、固定汲極電壓(Vd)之汲極電流(Id)-閘極電壓(Vg)的電壓關係、元件各式薄膜等霍爾量測進行分析。
本實驗的主動層主要分為兩種主動層結構:第一種主要為共摻雜氧化鋅與氧化鎵之主動層;第二種主要為多層結構(multilayer)的氧化鋅/氧化鎵/氧化鋅/氧化鎵/氧化鋅之主動層,其為五層疊加的半導體層。並根據此兩種結構再做退火溫度的不同、鍍氧化鎵時磁控濺鍍機(sputter)的參數改變來獲得載子遷移率(μ_FE)的提升,並以此兩種部分與前人所做的元件主動層為氧化鋅和氧化鎵在磁控濺鍍機(sputter)下以兩種RF射頻功率共濺鍍所得元件特性結果做比較,發現在第二種的多層結構可以降低臨界電壓(Vth)與提升載子遷移率(μFE)。
在閘極金屬選用方面,共分為Ti/Al (30nm/70nm)與Ti/Al/Ti (30nm/40nm/30nm)兩種結構,此兩種閘極金屬總厚度一致為100nm,從實驗結果量測得知,不論如何主動層的氧化鋅與氧化鎵含量如何改變、或是元件的快速熱退火溫度為何,元件特性參數諸如載子遷移率(μ_FE)、臨界電壓(Vth)、次臨界值擺幅(S.S.)、介面缺陷密度(Nt)等,Ti/Al/Ti閘極金屬一致來的比Ti/Al為佳,故在閘極金屬的選用,以Ti/Al/Ti (30nm/40nm/30nm)金屬為佳。
在濺鍍氧化鎵時的氧氣流量變化方面,共分為Ar:O2=9:1.2、Ar:O2=9:1.5、Ar:O2=9:1.8三種氣體體積比的操作變因,且根據量測結果發現在Ar:O2=9:1.8時有最高的載子遷移率(μ_FE)及最低的臨界電壓(Vth),低的臨界電壓(Vth)代表元件達成開狀態時所需施加在閘極的電壓較低,故濺鍍氧化鎵的氧氣流量條件以Ar:O2=9:1.8為佳。
在共濺鍍氧化鋅與氧化鎵時,氧化鎵的射頻(Radio frequency,RF)瓦數變化方面,共分為60W、70W、80W三種,根據量測結果發現,雖然此三種射頻功率的變化之元件閘極金屬選用Ti/Al (30nm/70nm)合金,但是一致地得到在濺鍍氧化鎵的射頻選用80W時有較高的載子遷移率(μ_FE)、較低的次臨界值擺幅(S.S.)以及較低的介面缺陷密度(Nt)。故在濺鍍氧化鎵時,射頻(Radio frequency,RF)功率瓦數以80W為佳。
在主動層總厚度變化方面,共分為總厚度:20nm、30nm、40nm三種操作變因,此三種操作變因在汲極電流(Id)-汲極電壓(Vd)與汲極電流(Id)-閘極電壓(Vg)兩種關係圖皆可以看出明顯的飽和趨勢與開關現象,但是根據量測結果發現在總厚度為40nm時有最高的載子遷移率(μ_FE)、最低的臨界電壓(Vth)、最低的次臨界值擺幅(S.S.)以及最低的介面缺陷密度(Nt)等較佳元件參數,故主動層總厚度40nm為佳。
在元件快速熱退火(Rapid thermal annealing)的退火溫度變化方面,主要分為未退火、550℃、600℃、650℃、700℃等五種操作變因,從量測結果得知,無論是上述的閘極金屬選用差異、主動層的多層結構(multilayer)的氧化鋅與氧化鎵含量差異、主動層的氧化鋅與氧化鎵的共濺鍍(ZnO co Ga2O3)等結果來看,皆一致地發現元件經過退火後可以增加載子遷移率(μ_FE)。故在元件的製作中,主動層與閘極絕緣層(SiO2)一律須要經過快速熱退火(Rapid thermal annealimg)的製程,如此一來才可以降低氧化層(主動層、閘極絕緣層)內部的缺陷,進而增加載子遷移率(μ_FE),改善元件特性。
The purpose of this study mainly discusses the bottom gate structure of the metal structure, the active layer (semiconductor layer) grows in different materials to achieve the switching characteristics of the thin film transistor, and injects the gate metal structure, different oxygen flow rates, radio frequency (RF) power, and annealing of the component's overall rapid thermal annealing system (RTA) in different temperature, pure zinc oxide, pure gallium oxide, zinc oxide doped gallium oxide. Then analysis the drain current (Id) relationship between drain voltage (Vd) under different gate voltages (Vg), the voltage relationship between the gate current (Id) and the gate voltage (Vg), and the Hall measurement of various thin films of the device.
[1.1] 施敏, 李明逵, “半導體元件物理與製作技術”, 交通大學出版社, 第三版, (2013年8月)
[1.2] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage, “IEEE Int. Electron Devices Meeting Tech. Dig., pp.521-524, (1995)
[1.3] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories. I: Device design and fabrication”, IEEE Transcations of Electron Devices, vol. 49, pp. 1606-1613, (Sep. 2002)
[1.4] Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories. I: Device design and fabrication”, IEEE Transcations of Electron Devices, vol. 49, pp. 1614-1622, (Sep. 2002)
[1.5] S. H. Noh, W. Choi, M. S. Oh, D. K. Hwang, K. Lee, and S. Im, S. Jang and E. Kim, “ZnO-based nonvolatile memory thin-film transistors with polymer dielectric/ferroelectric double gate insulators, “Appl. Phys. Lett., vol. 90,pp. 253504-253507, (2007)
[1.6] C. H. Park, G. Lee, K. H. Lee, S. Im, B. H. Lee, and M. M. Sung, “Enhancing the retention properties of ZnO memory transistor by modifying the channel/ferroelectric polymer interface”, Appl. Phys. Lett. Vol. 95, pp. 153502-153504, (2009)
[1.7] S. Chen, X. M. Cui, S. J. Ding, Q. Q. Sun, T. Nyberg, S. L. Zhang, and W. Zhang, “Novel Zn-Doped Al2O3 Charge Storage Medium for Light-Erasable In-Ga-Zn-O TFT Memory”, IEEE ELECTRON DEVICE LETTERS, Vol. 34, pp. 1008-1010, (Aug. 2013)
[1.8] J. Y. Bak, M. K. Ryu, S. H. K. Park, C. S. Hwang, and S. M. Yoon, “Impact of Charge-Trap Layer Conductivity Control on Device Performances of Top-Gate Memory Thin-Film Transistors Using IGZO Channel and ZnO Charge-Trap Layer”, IEEE TRANSCATIONS ON ELECTRON DEVICES, vol. 61, pp.2404-2411, (July. 2014)
[1.9] Y. Li, Y. Pei, R. Hu, Z. Chen, Y. Ni, J. Lin, Y. Chen, X. Zhang, Z. Shen, J. Liang, B. Fam, G. Wang, and H. Duan, “Charge Trapping Memory Characteristics of Amorphous-Indium-Gallium-Zinc Oxide Thin-Film Transistors With Defect-Engineered Alumins Dielectric”, IEEE TRANSCATIONS ON ELECTRON DEVICES, vol. 62, pp. 1184-1188, (April 2015)
[1.10] A. Janotti and C. G V. Walle, “Fundamentals of zinc oxide as a semiconductor”, IOP science, Rep. Prog. Phys. Vol. 72, pp. 126501-126529, (2009)
[2.1] 戴亞翔, “TFT-LCD 面板的驅動與設計”, 五南出版社, (2008)
[2.2] A. Janotti, C. G. V. Walle, “Fundamentals of zinc oxide as a semiconductor”, IOP science, Rep. Prog. Phys. Vol.72, (2009)
[2.3] Z. L. Wang, “Zinc oxide nanostructures: growth, properties and applications”, PHYSICS: CONDENSED MATTER, vol. 16, (2004)
[2.4] A. Janotti and C. G. V. Walle, “Oxygen vacancies in ZnO”, Appl. Phys. Lett. Vol. 87, (2005)
[2.5] J. K. Jeong, H. W. Yang, J. H. Heong, Y. G. Mo and H. D. Kim, “Origin of threshold voltage instability in indium-gallium-zinc oxide thin film Transistors.” Appl, Phys. Lett., vol. 93, (2008)
[2.6] C. H. Ahn, M. G. Yun, S. Y. Lee, and H. K. Cho.” Enhancement of Electrical Stability in Oxide Thin-Film Transistors Using Multilayer Channels Grown by Atomic Layer Deposition”. IEEE TRANSCATIONS ON ELECTRON DEVICES, vol. 61, (Jan 2014)
[2.7] W. Ts. Chen, S. Y. Lo, S. C. Kao, H. W. Zan, C. C. Tsai, J. H. Lin, C. H. Fang, and C. C. Lee, “Oxygen=Dependent Instability and Annealing/Passivation Effects in Amorphous In-Ga-Zn-O Thin-Film Transistors”, IEEE ELECTORN DEVICE LETTERS, vol. 32, (Nov. 2011)
[2.8] H. Bian, S. Ma, A. Sun, X. Xu, G. Yang, S. Yan, J. Gao, Z. Zhang, H. Zhu, “Improvement of acetone gas sensing performance of ZnO nanoparticles”, Alloys and Compoundsm, vol. 658, (2016)
[2.9] D. A. Neamen, “Semiconductor Physics and Devices Basic Principles”, Third Edition, (2012)
[2.10] 桑崇陞, “臨界電壓可調式延伸閘極電晶體脂生醫感測研究”, 交通大學碩士論文, (2013年4月)
[2.11] 張鼎張, 蔡宗鳴, 張冠張, 朱天健, 徐詠恩, “氧化矽基電阻式記憶體”, 專利, 第18卷第2期, (2012年12月)
[2.12] S.M. Sze,Kwok K. Ng, “Physics of Semiconductor Devices”, Third Edition, (2006)
[2.13] S. M. Sze, “Physice of semiconductor device” , New York: John Wiley & Sons, second ed. (1981)
[2.14] A. C. Tickle, “Thin Film Transistors” ,New York: Wiley & Sons, (1969)
[2.15] D. K. Schroder, “Semiconductor Material and Device Characterization”, A wiley-Interscience Publication, Arizona (1998)
[2.16] 蔡紓婷, “介面修飾對有機薄膜電晶體元件特性之影響”, 交通大學碩士論文, (2007年8月)
[2.17] J. K. Jeong, J. H. Jeong, H. W. Yang, J. S. Park, Y. G. Mo, and H. D. Kim, “High performance thin film transistors with cosputtered amorphous indium gallium zinc oxide channel,” Appl. Phys. Lett., 91, 113505, (2007)
[2.18] J. B. Bellam, M. A. Ruiz-Preciado, M. Edely, J. Szade, A. Jouanneaux and A. H. Kassiba, “Visible-light photocatalytic activity of nitrogen-doped NiTiO3 thin films prepared by a co-sputtering process,” RSC Advances., vol. 5, 10551, (2015)
[2.19] 余典衛, “保溫材鈣金屬污染對閘極氧化層的影響之影響及防治”, 交通大學碩士倫文, (2010)
[2.20] 施敏, 李明逵, “半導體元件物理與製作技術”, 交通大學出版社, 第三版, (2013年8月)
[4.1] 施敏, 李明逵, “半導體元件物理與製作技術”, 交通大學出版社, 第三版, (2013年8月)
[4.2] M. Chen, Z. L. Pei, X. Wang, C. Sun and L. S. Wen “Structural, electrical, and optical properties of transparent conductive oxide ZnO:Al films prepared by dc magnetron reactive sputtering”, J. Vac. Sci. Technol. A, vol. 19, pp.963-970, (2001)
[4.3] B. Y. Oh, M. C. Jeong, W. Lee and J. M. Myoung “Properties of transparent conductive ZnO:Al films prepared by co-sputtering”, J. Cryst. Growth, vol. 274, pp.453-457, (2005)
[4.4] S. Zimin, L. Litian, L. Zhijian, “Seld-heating effect in SOI MOSFETs,” IEEE Solid-State and Integrated Circuit Technology International Conference, pp.572-574, (1998)
[4.5] C. J. Park, Y. W. Kim, Y. J. Cho, S. M. Bobade and D. K. Choi, “The effects of Rapid Thermal Annealing on the Performance of ZnO Thin-Film Transistors.” Korean Physical Society, vol. 55, pp. 1925-1930, (Nov 2009)
[4.6] C. W. Liu, Chang, S. Jinn, “Optoelectronic and Structure Properties of Diluted Magnetic Semiconductor Based on ZnO Nanorods,” Item 987654321/150613, (2014)
[4.7] S. M. Sze, Kwok K. Ng, “Physics of Semiconductor Devices”, Third Edition, (2006)
[4.8] C. Bayram, J. L. Pau, R. McClintock, and M. Razeghi “Delta-doping optimization for high quality p-type Gan” JAP 104, 083512, (2008)
校內:2023-07-31公開