處理器的設計逐漸由高時脈的單一核心轉向多核心架構，因此多核心架構的處理器也日漸成形。隨著越來越多核心放入一個處理器，設計一個多核心處理器也越來越困難，因為多個核心之間的溝通、資料傳遞，常常是系統效能的瓶頸所在。因此提供一個測試傳輸效能的模擬平台將有助於多核心處理器的開發。SystemC中的交易層級模型(Transaction Level Modeling; TLM)能用比暫存器轉移層次(Register Transfer Level; RTL)更為抽象的方式來描述系統。這個層級主要模擬的是系統中的資料流動。多核心處理器架構中的核心和傳輸方式可以利用SystemC的模組及通道來設計。因此我們實作出一個基於SystemC的多核心架構模擬平台，模擬平台主要是藉由模擬多核心系統運作來計算核心之間的資料傳輸次數及資料傳輸量。最後我們將H.264/AVC編碼器於這個模擬平台上運作，為了測試各種多核心的傳輸架構，這邊利用平台建立的三種網路拓樸(Topology)來模擬，三種網路拓樸包含了網狀(Mesh)拓樸、環狀(Ring)拓樸及星狀(Star)拓樸。模擬平台提供了各個core之間的傳輸次數及傳輸量於三種網路拓樸，使用者可以依據這些資訊來探討各種演算法運作於不同多核心架構下的效能。

The concept of designing a processor has been transferred from a single-core processor to a multi-core processor. With more and more cores are implemented on a processor, to design a multi-core processor is more difficult because the communication between multiple cores often causes a performance bottleneck. Hence, a simulator which provides the communication times and communication capacity will help the development of a multi-core processor. Transaction level Modeling (TLM) in SystemC is a more abstract approach to modeling systems than register transfer level (RTL). It mainly models the data flow of the system architecture. The core and communication architecture on a multi-core processor can be simulated by the module and channel of SystemC. Therefore, we implement a multi-core architecture simulator based on SystemC in this thesis. The simulator provides the communication times and communication capacity by simulating the operation of multi-core systems. Finally, we port the H.264/AVC encoder on the simulator. To test the performance of several multi-core processor architectures, the three kinds of network topology, including Network-on-Chip topology, ring topology and star topology is adopted. The simulator provides the communication times and communication capacity between each core in the three types of network topology, which can be used to explore the performance of the parallel algorithm using different multi-core processor architecture.

[1] OSCI TLM-2.0 User Manual, http://www.systemc.org, June 2008
[2] SystemC. Available :http://www.systemc.org.
[3] S. Swan, "An Introduction to System Level Modeling in SystemC 2.0", Open SystemC Initiative (OSCI) Whitepaper, 2001.
[4] A. Donlin, "Transaction level modeling: Flows and use models," in Proc. of ACM/IEEE CODES + ISSS, 2004, pp. 75–80.
[5] "Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 14 496-10 AVC," Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVTG050, May, 2003.
[6] T. Wiegand, G. J. Sullivan, G. Bjntegaard, and A. Luthra, "Overview of the H.264/AVC video coding standard," IEEE Transactions on Circuits and Systems for Video Technology , vol. 13, no. 7, pp. 560-576, 2003.
[7] Hammond .L., Hubbert B., et al. " The Stanford Hydra CMP, " IEEE Micro, 2000, 20(2):71-84.
[8] "Cell Broadband Engine Architecture and its first implementation", IBM developerWorks, November 29, 2005.
[9] 簡榮胤, 應用資料流模型於 IBM Cell寬頻引擎處理器之開發環境,國立成功大學資訊工程學系, 碩士論文, 2009.
[10] B. Malloy, E. Lloyd and M. Soffa, "Scheduling DAG"s for Asynchronous Multiprocessor Execution, " IEEE Trans. Parallel and Distributed Systems, vol. 5, no. 5, May 1994.
[11] J. Chong, N. R. Satish, B. Catanzaro, K. Ravindran, and K. Keutzer,"Efficient parallelization of h.264 decoding with macro block levelscheduling," in IEEE International Conference on Multimedia and Expo,July 2007, pp. 1874–1877.
[12] C. Meenderinck, A. Azevedo, M. Alvarez, B. Juurlink, and A. Ramirez. "Parallel Scalability of H.264" In: Proc. First Workshop on Programmability Issues for Multi-Core Computers, January 2008.
[13] A. Azevedo, C. Meenderinck, B. Juurlink, A. Terechko, J. Hoogerbrugge, M. Alvarez, A. Ramirez, "Parallel H.264 Decoding on an Embedded Multicore Processor", in Proceedings of the 4th International Conference on High Performance and Embedded Architectures and Compilers, Paphos, Cyprus, January 2009.
[14] Groth, David, Toby Skandier, "Network+ Study Guide, Fourth Edition". Sybex, Inc. 2005