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研究生: 林郁翔
Lin, Yu-shang
論文名稱: 時間觸發型混合數據匯流排技術發展之小型飛機數位航電系統
Development of time triggered hybrid data bus system for small aircraft digital avionic system
指導教授: 林清一
Lin, Chin-E
學位類別: 碩士
Master
系所名稱: 工學院 - 航空太空工程學系
Department of Aeronautics & Astronautics
論文出版年: 2007
畢業學年度: 95
語文別: 英文
論文頁數: 78
中文關鍵詞: 時間觸發混合數據匯流排
外文關鍵詞: Hybrid data bus, TTCAN
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  • 數位通訊現今發展日新月異,在實務應用方面極為廣泛,而數位航電亦為如此。數位航電系統發展至今,線上可換式單元以及整合式模組的航電的建置,使系統架構在設計上更有彈性與簡化,本文延續控制區域網路(CAN)的匯流排系統建置在小型飛機數位航電系統的相關研究,針對資料傳輸時間的可預測做了相當程度的強化。CAN匯流排系統係採用事件觸發的傳輸模式,資料傳輸的正確性與可靠性已有不錯的成果。基於CAN優先權機制的特性,通常高優先權隸屬於較高頻率的訊息或是重要的即時訊息。雖然能保護到較高優先權的訊息,不過這樣會造成低優先權的訊息傳輸時間將不可被預期,甚至發生傳輸負載量過高造成訊息遺失的問題;對於訊息傳輸時間的不可預期性,許多研究皆採用時間觸發的整合晶片TTCAN來發展匯流排系統,有了時間規劃的排程,傳輸資料與接收資料將會在分配的時間內運行,然而TTCAN匯流排系統較適合週期性的訊息傳輸,依使用者要求,時間排程規劃有絕對的嚴謹性。
    本研究的目的在於分類各訊息的頻率與時間排程觀念來發展混合數據匯流排系統,由於TTCAN整合晶片對時序的同步化複雜性甚高,在發展上有其相對的成本負擔與複雜性。本文針對TTCAN資料傳輸可預期優點,不採用TTCAN晶片而在先前dual bus CAN匯流排系統架構下植入時間觸發之概念,如此可避免複雜的同步傳輸問題,並可達到資料傳輸的可預期性。

    Digital avionics using line replaceable unit (LRU) and integrated module avionics (IMA) has been promoted into very simplified and flexible design supports in modern system. Digital data bus system using controller area network (CAN) for small aircrafts has improved the accidental event by adding time trigger. However, the predictability on data transmission requires enforced. The arbitration mechanism in CAN has awarded higher priority to those high frequency data or important real time data. Some deficiency may cause unpredictable delays on lower priority message and data lose when high bus load situation. To integrate time trigger into Time Triggered CAN (TTCAN) chip can improve the time scheduling in periodic data transmission. Consequently, the complexity in time sequence synchronization has brought in significant load in development. This research method classifies the data frequency and assigning the concept of time to integrate hybrid data bus System. The research goal uses concept of TTCAN on dual bus CAN system and improve disadvantage of CAN.

    ABSTRACT i 摘 要 ii 誌 謝 iii LIST OF FIGURES vi LIST OF TABLES viii LIST OF ACRONYMS ix CHAPTER I INTRODUCTION 1 1.1 Introduction 1 1.2 Motivation 2 1.3 Procedure of Research 3 1.4 Organization of this thesis 4 CHAPTER II CONTROLLER AREA NETWORK AND DIGITAL AVIONICS SYSTEM 5 2.1 Controller Area Network and Hardware 5 2.1.1 History 5 2.1.2 Layered Structure of CAN Module 6 2.1.3 CAN Controller – SJA1000 9 2.1.4 CAN Transceiver – PCA82C250 11 2.1.5 The CAN IP Module Hardware Describe 12 2.2 Frame Type 14 2.2.1 Data Frame 14 2.2.2 Arbitration 16 2.2.3 Error Detecting 17 2.3 Avionics System 19 2.3.1 ARINC 629 19 2.3.2 Summary of This Chapter 21 CHAPTER III TIME TRIGGERED CAN 22 3.1 Introduction 22 3.2 TTCAN Architecture 23 3.3 Elements of Protocol 25 3.3.1 The Reference Message 26 3.3.2 The Basic Cycle 27 3.3.3 The Matrix Cycle 28 3.3.4 Time Mark 29 3.4 The Time Window 30 3.4.1 Exclusive Time Windows 30 3.4.2 Arbitration Time Windows 30 3.4.3 Free Time Windows 30 3.5 Fault Tolerant TTCAN Network 31 3.6 The Work of TTCAN 33 3.6.1 Apply the System Matrix to Time Master 33 3.6.2 CAN and TTCAN 35 CHAPTER IV SYSTEM PROGRAM DESIGN 37 4.1 CAN IP Module Program Design 40 4.1.1 Firmware 40 4.1.2 Initialize SJA1000 40 4.1.3 Transmission 42 4.1.4 Reception 42 4.2 Hybrid Data Bus Transmission 43 4.2.1 Procedure for The Assignment CAN Identifiers 44 4.2.2 Building the System Matrix 47 4.2.3 Master Schedule Node and Receive Node 48 4.2.4 Summary This Chapter 53 CHAPTER V SYSTEM TEST AND ANALYSIS 54 5.1 Hardware Architecture 54 5.2 Transmission Time Analysis of CAN on Event Triggered Process 56 5.2.1 Node to Node Transmission Test with Bit Rate 100kbps 57 5.2.2 Arbitration Test with Bit Rate 100kbps 58 5.2.3 Arbitration Test with Bit Rate 500 kbps 61 5.3 HDB System Test Analysis 63 5.3.1 System Test Procedure 63 5.3.2 Test Result and Analysis 66 5.3.3 Development of Monitor MS Station 69 5.3.4 Implement the HDB System on The Digital Instrument 70 5.3.5 Summary This Chapter 71 CHAPTER VI CONCULSION 74 REFERENCES 76 VITA 78

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