現今的矽基互補式金氧半場效電晶體的技術發展已經面臨瓶頸，元件性能的提升越來越依靠材料與結構方面的進步，如矽鍺以及奈米片的使用。在此基礎之上，3D 堆疊 NMOS-on-PMOS 結構（也稱為 互補式堆疊電晶體，CFET）被提出來取代 FinFET 結構。採用單片或順序3D-IC整合的CFET已被實驗證明可以有效將標準單元尺寸減小多達50％，同時仍保持優異的性能。其中，晶圓鍵合技術被證實是一種可以實現垂直堆疊通道的技術。
在這篇論文中，我們通過晶圓鍵合的方式，製備了高品質的層轉移薄膜與完成了垂直的通道堆疊。晶圓鍵合須滿足足夠低的表面粗糙度，且要求表面具備親水性以實現在低溫下達到高鍵合強度。通過製程的優化，我們提出了兩種有無蝕刻終止層的鍵和製程，其結果可用於八吋晶圓規格。
此外由於鍺沒有穩定的俱生氧化物(GeO2)，導致在HKMG結構中容易出現高介面缺陷的情況，限制了Ge基元件的發展。在高溫下，Ge/GeO₂間容易形成低氧化態的一氧化鍺(GeO)，一旦GeO 脫附發生，GeO2 會變成不穩定，進而產生嚴重的閘極漏電。然而GeO₂作為介面層的優勢，又使得其幾乎無可替代。在本論文提出使用新型氮化前驅物—聯氨(Hydrazine, N₂H₄)，在GeO2的基礎上進行氮化。相較於較常見的氨氣(NH3)氮化處理，N₂H₄無須採用電漿製程，便可達到氮化介面層的效果，因此能有效降低表面損傷。經由電容結構以及材料分析進行驗證，表明N2H4是一種可以在鍺基結構上具備優異電性的新穎介面處理。
另一方面，通過晶圓鍵合技術，我們可以將高品質的鍺層轉移至諸多施主晶圓(host wafer)上，並製備諸如GeOI、異質Ge/Si CFET與異表面取向Ge/Ge CFET。其中透過轉換施主晶圓與供體晶圓(donor wafer)即可透過類似的工藝，將結構從單層結構變換為雙層結構或者多層結構。透過該方法，將施主晶圓從Si基板替換成SOI基板，製備了異質Ge/Si CFET；將施主晶圓從SOI基板替換成(100)表面取向的GeSOI基板，並將供體晶圓替換為(111)表面取向的GeSOI基板，製備了異晶向Ge/Ge CFET，所製備的元件均具備優異的性能。最後，我們針對本篇論文中的元件在低溫下的表現進行了完整的探討。驗證了通過採用層轉移的方式，製備的Ge基元件，具備優異的電晶體特性，標示著鍺基元件在低溫下亦可達到優異的電性。

For the state-of-the-art silicon-based CMOS FETs have reached a bottleneck, and the improvement of device performance increasingly relies on advances in materials and structures, such as the use of silicon germanium and nanosheets (NS) structure. Based on this development, the 3D stacked NMOS-on-PMOS structure (also called complementary stacked transistor, CFET) was proposed to replace the FinFET / NSFET structure. CFETs using monolithic or sequential 3D-IC integration have been experimentally demonstrated to be effective in reducing the standard cell size by up to 50% while still maintaining excellent performance. Among them, wafer bonding technique has been proven to be a emergent method that can achieve vertical stacking structure.
In this dissertation, we fabricated high-quality layer-transferred films and completed vertical channel stacking by wafer bonding. Wafer bonding must meet sufficiently low surface roughness and the surface must be hydrophilic to achieve high bonding strength at low temperatures. Through process optimization, we proposed two methods for bonding processes with and without etching stop layer, and the results can be used for 8-inch wafer specifications.
In addition, since germanium does not have a stable native oxide (GeO2), high interface defects are easily present in the HKMG structure, limiting the development of Ge-based devices. Moreover, low-oxidation germanium monoxide (GeO) is easily formed between Ge/GeO2 at high temperatures. Once GeO desorption occurs, GeO2 becomes unstable, resulting in severe junction leakage. However, the advantages of GeO2 as an interfacial layer make it almost irreplaceable. In this dissertation, we proposes the use of a new nitridation precursor, hydrazine (N2H4), to carry out nitridation based on GeO2. Compared to the more common ammonia (NH3) nitridation treatment, N2H4 can achieve the effect of nitriding the interfacial layer without the plasma process, thus effectively reducing surface damage. Verification through capacitor structure and material analysis shows that N2H4 is an acceptable interfacial treatment that can have excellent electrical characteristics on germanium-based structures.
On the other hand, through wafer bonding technology, we can transfer high-quality germanium layers to many host wafers and prepare GeOI, heterogeneous Ge/Si CFET and hetero-oriented Ge/Ge CFET. By converting the donor wafer and the host wafer, the structure can be changed from a single-layer structure to a double-layer structure or a multi-layer structure through a similar process. Through this method, the donor wafer was replaced from Si substrate to SOI substrate to fabricate heterogeneous Ge/Si CFET; the donor wafer was replaced from SOI substrate to (100)-oriented GeSOI substrate, and the donor wafer was replaced with (111)-oriented GeSOI substrate to fabricate hetero-oriented Ge/Ge CFET. The devices have excellent performance. Finally, we present a complete discussion of the performance of the devices in this dissertation at low temperatures. It was verified that the Ge-based devices fabricated by the layer transfer have excellent transistor properties, indicating that it is possible for germanium-based devices to achieve excellent electrical characteristics at low temperatures.

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