本論文旨在進行一種採用氧化矽鋯閘極介電層、具高載子移動率氮氧化鋅(ZnON)之通道層薄膜電晶體之開發，期藉由高載子移動率與高閘極控制力，大幅度提升元件電特性與可靠度。
本研究分為兩大部分，第一部分為接續本實驗室先前研製氧化矽鋯閘極介電層於氮氧化鋅通道層之應用，藉由摻入適量之矽原子於二氧化鋯介電層中，提升介電層品質並降低其與氮氧化鋅通道層之界面缺陷密度，並將進一步分析氮氧化鋅薄膜電晶體之電特性與可靠度之影響。第二部分為利用濺鍍沉積鋅薄膜過程適當控制氮氣與氧氣分壓開發氮氧化鋅薄膜，藉由調變各項濺鍍沉積參數(包括濺鍍功率、製程壓力與N2/Ar/O2氣體流量比)以改變氮氧化鋅通道層之組成成份與厚度。除將進行薄膜分析、元件電特性與可靠度之研究外，亦將探討ZnON通道層的熱退火製程對材料品質、元件電特性與可靠度之影響。
於本論文第一部分，首先比較二氧化矽與氧化矽鋯閘極介電層應用於氮氧化鋅薄膜電晶體情況下元件電特性與可靠度之差異。實驗結果顯示，相較於二氧化矽閘極介電層，採用摻入適量矽原子之二氧化鋯閘極介電層，可減少界面缺陷進而提高介面品質、具較佳之閘極控制力，且經600 oC退火後仍呈現非晶型態，於相同等效氧化層厚度下具較低漏電流。
於本論文第二部分，應用於TFTs通道層的ZnON薄膜，ZnON的形成主要是藉由適當製程引入高含量N原子取代ZnO的O原子，根據實驗結果證實，由於N3-比O2-具有較大尺寸及較高的p軌域能量，使a-ZnON能隙寬度降低，使大部分氧空缺移除，有效改善界面缺陷使閘極控制力大幅提升，降低載子移動受界面缺陷捕獲之機率，其漏電流降低而提升氮氧化鋅通道層之薄膜品質。另一方面，相較於一般非晶型氧化物半導體(AOS)，ZnON僅含單一金屬，僅需藉由薄膜內適C軸結晶氮化鋅(c-Zn3N2)及氧化鋅(ZnO)奈米晶粒的適當含量以降低缺陷濃度(載子濃度下降)，再利用其c-Zn3N2內電子具較小有效質量(m_e≈ 0.19m_0)之特點，可展現出較高的載子移動率。此外，進一步藉由熱退火處理以修補內部氮、氧空缺及活化氮氧化鋅薄膜之品質，而達成其元件特性與可靠度之優化。
實驗結果顯示，通入適當氣體流量之ZnON通道層內適Zn3N2及ZnO奈米晶粒，可改善薄膜的品質亦減少介電層/通道層界面之缺陷密度，亦有助於降低氧空缺之含量。本研究發現經300 oC氮氣環境下退火之N(19%)-ZnON TFT，展現最佳元件之特性與可靠度，其載子移動率為35.1 cm2/V∙s、次臨界擺幅為97 mV/dec、元件電流開關比為8.82×107、臨界電壓為0.35 V與界面缺陷密度為1.25×1012 cm-2eV-1；於正負偏壓應力測試實驗部分，臨界電壓偏移量分別為0.18 V和-0.15 V；於照光負偏壓應力部分，臨界電壓偏移為-0.18 V；於熱穩定度部分，其臨界電壓偏移量為-0.15 V。
本實驗成功以共濺鍍技術製備矽摻雜二氧化鋯介電層及氮氧化鋅鋅通道層之薄膜電晶體，具較高載子移動率，且成功改善其漏電流、界面品質、閘極控制能力、元件特性與可靠度，此材料系統具備高驅動及低功耗等優良特性，將有助於未來顯示技術之應用以及電子產品性能之提升。

ZnON TFTs with high-κ material as gate dielectrics, which both the channel layer and dielectric layer use a RF sputtering process, were fabricated and investigated in this work. To incorporate Si in high-κ dielectric layer can suppresses oxygen vacancies and immunity of crystal-structured at post-deposition annealing (600°C) to decrease surface roughness. In addition, to incorporate N in ZnO channel could be reduce the channel defect density and has excellent electrical properties and stability. In this work, we used high mobility and high carrier concentration of ZnON to apply in High-k dielectric layer to improve the operating voltage and then enhance the gate control ability. Experimental results reveal that Zr0.85Si0.15O gate dielectric combine with N(19%)-ZnON channel layer by post deposition annealing (PDA) in N2 at 300ºC exhibit the best device performances with the subthreshold swing of 97 mV/dec, field effect mobility of 35.1 cm2/V∙s, on/off current ratio of 8.82×107, the threshold voltage shift after 1000 sec positive/negative gate bias stress of 0.18 V/-0.15 V, and the threshold voltage shift after 1000 sec negative bias illumination stress of -0.18 V.

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