隨金屬氧化物半導體場效應電晶體的尺寸進入奈米等級時，為增進元件性能,提昇載子的移動率，應變工程和提高閘極的介電質已漸成為金屬氧化物半導體場效應電晶體前段製程量產的必要技術。 本論文中對淺溝槽隔離層應變工程和氮氧化矽閘極的介電質做更完整的探討，並提出數種新的淺溝槽隔離層的先進應變工程方法和不同濃度的氮含量氮氧化矽閘極的介電質。除外，在金屬氧化物半導體場效應電晶體前段製程其多晶矽閘極晶粒結構和蝕刻技術亦是奈米等級電晶體量產必要技術之一，在此我們也提出改良製作閘極之技術，此技術非常符合奈米等級晶片製程。本論文將先進應變工程及改良之閘極成長與蝕刻技術運用於提昇奈米金屬氧化物半導體場效應電晶體元件之特性以驗証其實用性。
首先探討應變技術對元件的效能之影響，在本論文中討論到如何利用改良後的淺溝槽隔離層製程技術和新的溝槽的內壁上利用氮氣離子體二氧化矽介質摻雜氮成長之氮氧化矽層內襯，結果發現淺溝槽絕緣層應力在不同主動區擴散長度下對金屬氧化物半導體場效應電晶體的遷移率有不同之影響。而且，在此技術下因為應用了淺溝槽隔離層的應力而降低來至於淺溝槽隔離層井壁造成能帶穿遂效應退化引起的金屬氧化物半導體場效應電晶體元件接面漏電流和基材漏電流. 在改良的淺溝槽隔離層製程技術中，在製程上淺溝槽隔離層與鄰近電晶體主動區的高度差可被有效的改善。在電性上，我們發現由接面所造成的基材漏電流可被有效的降低。由擴散長度效應中，其溝槽隔離層的壓應力可被可降低進而改善N型金屬氧化物半導體場效應電晶體的劣化。如此，使用優化的溝槽隔離層製程技術可降低漏電流而且不會犧牲遷移率而造成驅動電流不足。在新的溝槽的內壁上利用氮氣離子體二氧化矽介質摻雜氮成長之氮氧化矽層內襯去取代傳統的二氧化矽內襯中，我們發現接面和次臨界區漏電流可被有效的降低。本論文亦應用此技術於靜態隨機存取存儲器中，亦發現靜態隨機存取存儲器的效能也被改善。在多晶矽的材質上本論文利用不同的成長氣體去成長多晶矽閘極。 由實驗結果中可知改良的多晶矽閘極可改善當閘極介層厚度越薄，因通道電荷所引發在多晶矽閘極的空乏效應且多晶矽薄膜表面的粗糙度亦可被有效的降低。且在金屬氧化物半導體場效應電晶體電性上，可改善汲極飽和電流和漏電流和短通道效應。且在本論文中亦把此技術應於靜態隨機存取存儲器中也對其作研究探討。在多晶矽下的閘極介電質，於六十五、四十五及四十奈米製程技術下的製程是利用氮氣離子體二氧化矽介質摻雜氮的技術去成長不同摻雜氮濃度的氮氧化矽。本論文中深入探討對元件特性和可靠度的影響。在元件效能和可靠度取得平衡。在後續製程中則是整個多晶矽閘的蝕刻，而如何優化多晶矽閘蝕刻製程則是一個重點。本論文則探討在改良的多晶矽閘的蝕刻可去除成長多晶矽時造成的多晶矽凸起物缺陷且亦可改善元件電性。所以，本論文主旨說明了金屬氧化物半導體場效應電晶體前段製程對元件特性的改善和深入的探討。

In this dissertation, we study the impact of strain engineering and poly gate technologies on nano meter scale MOSFETs performances in detail. The study is divided in five parts. In the chapter 2, we propose improved STI process on MOSFET technology. Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced CMOS technology. This study presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in SRAM. The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obviously decrease of BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion (LOD) effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. In order to study more mechanical stress of STI, the novel SiON liner was grown by decoupled-plasma-nitridation (DPN) to replace pure SiO2 liner by in-situ steam generation (ISSG). The chapter 3 discusses the benefits of SiON liner growth by DPN and SiON liner induced stress compared to conventional pure oxide liner growth by ISSG. Thin STI SiON liner offers lower sub-threshold leakage current without drive current loss for transistor performance. Moreover, junction leakage current is also reduced with scaling device active area. This chapter demonstrates the influences of thin STI SiON liner growth by DPN in STI manufacture. In the chapter 4, an improved design for the polycrystalline gate is developed for 65nm low power CMOS technology. Using the fine-grain poly deposition, less poly depletion effect and decrease of the electrical gate dielectric thickness can be obtained. Also, the novel poly deposition successfully reduces the roughness of poly surface and produces smaller poly grain size after subsequent rapid thermal processing (RTP) steps. Meanwhile, the improved poly deposition can suppress short channel effect (SCE) and reduce off-state leakage current. The fine-grain poly deposition results in a better VRDB (Voltage Ramp Dielectric Breakdown) and uniformity on specific test vehicle. We have a detail discussion with fine-grain poly deposition in this chapter. In the chapter 5, In order to obtain a clear perspective concerning the time-dependent-dielectric-breakdown (TDDB) and negative bias temperature instability (NBTI) issue of P-MOSFETs, the ultra-thin gate dielectric with various effective RF powers of DPN SiON films was discussed in this chapter. In this chapter, we found that more nitrogen dose in SiON by DPN effective RF power adjustment can effectively suppress boron penetration and improve MOSFETs performance. However, it made a great impact on TDDB and NBTI. Therefore, it is important to adjust nitrogen dose by DPN effective power to balance the both. In the chapter 6, a novel poly etching method and the effect of poly pimple defect induced device mismatch on static-noise-margin (SNM) and minimum operation voltage (Vcc_min) of low-power 6T-SRAM is presented. The novel poly etching offers a straight and uniform poly profile without poly pimple defect. The improvement on circuit level is examined by the yield of scan chain and memory-built-in-self-test (MBIST) which is known to correlate well to process induced defects. The novel poly etching also improves the device mismatch and uniformity. From chapter 2 to chapter 6, the mechanical strain engineering was modulated via related STI process change and poly gate engineering technologies were also discussed by fine-grain poly growth and improved ultra-thin gate dielectric at sub-micron MOSFET technologies. In this dissertation, our researches involved widely whole major sub-micron front-end MOSFET technologies.

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