近來由於類神經網路系統的崛起，許多無機氧化物薄膜電晶體元件被應用於人工腦神經及突觸連結的操作，透過外在刺激（例如：電或光脈衝）調控元件的電流大小，藉此模擬出突觸權重上的變化，並且可將其整合於類神經運算系統中運作，實現同步運算及記憶的高效能網絡。
　　薄膜電晶體元件若使用鐵電薄膜作為介電層，除了具有高介電常數外，可藉由極化現象影響主動層載子聚集和空乏特性來控制電流的傳輸，與傳統的無機氧化物薄膜電晶體中載子被界面缺陷捕捉/釋放(Charge Trapping/ Detrapping)機制最大的差別在於：元件在極化後的組態可以在移除刺激後受到殘留的極化效應依舊被保留，除非再度施加足夠的偏壓反轉鐵電中的極化方向，元件組態才會受到影響，無疑的鐵電極化特性提升了元件組態的維持能力，強化了人工突觸特性中的長期可塑性展現及記憶能力。
　　吾人使用以溶膠凝膠法製備氧化鋅錫薄膜電晶體，並在其上加上一層聚偏二氟乙烯－三氟乙烯(P(VDF-TrFE))的高分子鐵電層，雖然此高分子鐵電層並非介電層，但仍可受到閘極偏壓而產生鐵電耦合效應；本研究主要目的即為比較元件受到鐵電耦合作用，與未覆加高分子鐵電層的氧化鋅錫薄膜電晶體電性差異以及在突觸可塑性上表現出的優勢。
　　第一部份吾人透過元件的電晶體基本轉換曲線特性(ID-VG)量測，分析加上P(VDF-TrFE)的氧化鋅錫薄膜電晶體與一般氧化鋅錫薄膜電晶體的電性差異：在覆加了P(VDF-TrFE)的元件中，受其偶極排列的影響，在正及負閘極偏壓下，分別受到氟離子與質子作用而強化了氧化鋅錫主動層之電子在界面缺陷被捕捉及釋放的效應，並因為電子被捕捉的效應被強化，使得覆加了P(VDF-TrFE)的元件在正偏壓下具有相對較小的讀取電流值。
　　第二部分則為對元件施加外在閘極電脈衝刺激，模擬多項突觸性質的操作。首先吾人先針對元件們進行單極性的連續性電脈衝刺激，確保元件隨著刺激具有逐漸增益及抑制電流的行為，做為突觸元件上的權重變化；再來吾人開始對元件進行一連串突觸可塑性的相關操作，發現覆加上P(VDF-TrFE)的元件在突觸功能上相較於一般氧化鋅錫薄膜電晶體：在成對脈衝增益表現更貼近生物突觸的特性；並在連續增益及抑制行為中，具備更多的有效組態數及提升線性程度。而在短期製長期記憶轉換的操作實驗中，亦只有加上完全退火(140°C)處理後的覆加P(VDF-TrFE)元件在不同程度下的刺激程度後，具備逐漸強化突觸後電流的維持能力特性。結果顯示覆加P(VDF-TrFE)的元件在接受閘極電脈衝刺激之後，因為P(VDF-TrFE)的偶極排列所引發出的殘留極化能力，強化了氧化鋅錫主動層的電子被捕捉或是被釋放效應，使得元件的組態在讀取狀態下仍被維持住、並反映於電流的增益與抑制比例上升情形中，說明此類結構更適合於人工突觸元件的應用。最後吾人更單獨使用該元件進行脈衝時序依賴可塑性操作，藉由同時控制突觸前端（元件閘極端）及後端（汲極端）的脈衝波型和時序，成功控制突觸權重的變化，並做出典型的赫布學習型曲線分布。

Nowadays, based on the growth and development of artificial neural network systems, the memory characteristics of transistor devices are also taken into considerations. More AOS TFT-based synapses are selected as hardware devices for neuromorphic computing. Also, there is a trend of replacing the original gate dielectric layer with ferroelectric material, which also possesses high-k property and furthermore, the polarization effect. In this study, spin-coated ZTO TFT devices are fabricated for the measurement of electrical properties and the comparison of ferroelectric layer P(VDF-TrFE) coupling or not are also taken into discussion. In the first part we focus on the transfer characteristics of each TFT device. Charge trapping/detrapping mechanism in channel/gate dielectric interface can be further enhanced with dipole effect in P(VDF-TrFE). With more electron trapped induced by fluorine repulsion, a reduced readout current is obtained under positive bias. For, synapse emulation, gate and drain terminals of devices are treated as pre- and post-synapse sites of biological synapse and the measured drain current can be considered as synapse weight. In PPF and potentiation/ depression cycles measurement the results of the ZTO TFT device with fully annealed P(VDF-TrFE) addition always exhibit better property than that of the original ZTO TFT devices. On top of that, our fully-annealed P(VDF-TrFE) coupled ZTO TFT demonstrates STM to LTM transition characteristics, attributed to the partial polarization effect. Last but not least, we operate the STDP measurement with fully annealed P(VDF-TrFE) couples ZTO TFT device and perform an typical asymmetric Hebbian learning behavior.

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