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研究生: 魏宏儒
Wei, Hung-Ju
論文名稱: 應用於直接升頻系統之雙閘極混頻器與低電壓折疊式混頻器設計與實作
Design and Implementation of Dual-Gate Mixer and Low-Voltage Folded Mixer for Direct Up-Conversion System
指導教授: 王永和
Wang, Yeong-Her
洪茂峰
Houng, Mau-Phon
王是琦
Wang, Shyh-Chyi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2005
畢業學年度: 93
語文別: 中文
論文頁數: 75
中文關鍵詞: 直接升頻系統雙閘極混頻器折疊式低電壓
外文關鍵詞: Direct Up-Conversion System, Folded, Low Voltage, Dual-Gate, Mixer
相關次數: 點閱:126下載:3
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  • 一般傳統無線通訊射頻前端電路所採用的是外差(heterodyne)的架構,然而此架構需要兩個以上用來升頻的本地震盪器,以及需要濾波器去除不必要的旁波帶訊號,因此並不利於高度的RFIC整合。然而避免這個問題的最佳方式是採用直接升頻的架構,乃是將射頻載波直接施於正交調制器,便可以消除中頻的電路部分,以節省面積、成本、功率消耗以及設計時間,大幅簡化射頻電路的複雜度。

    本論文主要以TSMC 0.18um 1P6M CMOS製程成功研製將低頻1MHz訊號直接升頻至2.4GHz ISM頻帶的雙閘極混頻器與低電壓混頻器。其中低電壓混頻器是延續雙閘極混頻器的基本設計概念,結合主動雙閘極與被動場效電晶體的混頻機制,設計出新式直接升頻混頻器;因為採用折疊式(Folded)的架構,所以在1V的低電壓便能提供轉換增益,模擬結果也顯示此新式的混波架構具有非常理想的輸入/輸出端隔離度和低雜訊等特性。同時,現今通訊系統產品漸以平衡式或差動式的電路為設計,因此在論文中也將討論平衡式元件的量測方法以及實作電路。

    The traditional communication RF front-end circuit applies the heterodyne structure generally. Because this structure needs more than two up-conversion local oscillators and some filters to eliminate spurious signal, it is not advantaged to the high integration of RFIC. The Best method to avoid such a problem is to use direct up-conversion structure which adds RF carrier to quadrature modulator, so it can remove IF circuits to save the area, cost, power consumption and time-to-design.

    This thesis uses TSMC 0.18um 1P6M CMOS process to implement the “Dual-Gate Mixer” and “Low-voltage Mixer” which transforms 1MHz signal up to 2.4GHz ISM band directly. The low-voltage mixer based on the basic design concept of Dual-Gate mixer is a novel structure which combines the mixing machines of “Active Dual-Gate Mixer” and “Passive FET Transistor”. Because of “Folded Structure”, the mixer can provide conversion gain at low voltage (1V). From the results of measurement, very good input/output isolation and low noise can be achieved. As the trends of the communication system are according to “Balanced and Differential structure”, the measurement of the balanced devices and circuits design will be also discussed.

    第一章 簡介 1 1.1 無線通訊發展現況 1 1.2 CMOS RF 趨勢 2 1.3 研究動機 4 1.4 章節介紹 5 第二章 基本理論 6 2.1 發射系統架構 6 2.1.1 直接升頻架構 7 2.1.2 Two-Stage 升頻架構 9 2.2 混頻器的基本理論 10 2.2.1 乘法的混波機制 11 2.2.2 非線性產生的混波機制 12 2.3 混頻器的規格參數 17 2.3.1 轉換增益/損耗 18 2.3.2 1dB壓縮點 18 2.3.3 輸入端三階交錯點 19 2.3.4 雜訊指數 21 2.3.5 隔離度 22 第三章 雙閘極混頻器 23 3.1 架構簡介 23 3.2 設計原理 24 3.2.1 雙閘極電路架構 24 3.2.2 設計流程圖 27 3.3 平衡轉非平衡被動電路 28 3.3.1 環型耦合器 28 3.3.2 LC Balun(1MHz) 31 3.3.3 方向耦合器 33 3.3.4 鎊線(Bondwire)的模擬 34 3.4 模擬結果 35 3.5 電路佈局 38 3.6 晶片測試 40 3.5.1 測試印刷電路板(PCB) 40 3.5.2 DC直流偏壓量測 41 3.5.3 小訊號直流偏壓量測 45 3.7 結果討論 48 第四章 低電壓折疊式混頻器 51 4.1 架構簡介 51 4.2 設計原理 53 4.2.1 電路設計方法 53 4.2.1 電路設計特點 55 4.3 模擬結果 56 4.4 電路佈局 60 4.5 晶片測試 61 4.5.1 測試印刷電路板(PCB) 61 4.5.2 DC直流偏壓量測 62 4.5.3 小訊號直流偏壓量測 64 4.6 結果討論 67 第五章 結論 69 參考文獻 71 作者簡介 75

    [1]P. R.Gray and R. G.Meyer, “Future directions in silicon ICs for RF personal communications,” Proc. IEEE Custom Integrated Circuits Conf. (CICC), pp. 83-90, 1995.

    [2]邱煥凱, “2.4-2.5GHz ISM 頻帶砷化鎵微波單石積體電路晶片組之研製,” 國立台灣大學電機工程研究所博士論文, 1997.

    [3]IEEE Std 802.11a/D7.0-1999,“Part11: Wireless LAN Medium Access Comtrol (MAC) and Physical Layer(PHY) Specification: High-speed Physical Layer in the 5GHz Band.”

    [4]ETSI, “Broadband Radio Access Network (BRAN); HIPERLAN type 2 technical specification; Physical (PHY) Layer,” Aug. 1999.

    [5]A.Boveda, F.Orgitoso, and J. I.Alonso, “A 0.7–3 GHz GaAs QPSK/QAM direct modulator,” IEEE J. Solid-State Circuits, vol. 28, pp. 1340-1349, 1993.

    [6]R. Cushing, “800 to 250MHz single-sideband upconversion of quadrature DDS signals,” Technical Note, Analog Deviced Co., 1999.

    [7]S. A. Maas, Microwave Mixer, Artech House, 1993.

    [8]Jian-Ming Wu, Monolithic-Microwave Integrated-Circuit Design of Quadrature Modulator for Wireless Communications, NSYSU Master Thesis, 1999.

    [9]A. R. Behzad, et al., “A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard,” IEEE J. Solid-State Circuits, vol. 38, pp. 2209-2220, Dec. 2003.

    [10]Marc A.F. Borremans and Michiel S.J. Steyasert, “A 2-V, Low Distortion, 1GHz CMOS Up-Conversion Mixer ”, IEEE Journal of Solid-State Circuits, Vol. 33, No.3, pp.359-366, March 1998.

    [11]J.C. Rudell, J.-J.Ou, T. B. Cho, G. Chien, F. Brianti, J.A. Weldon, and P.R. Gray, “A 1.9GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Application,”IEEE Journal of Solid-State Circuits, Vol. 32, No. 12, pp. 2071-2088, December 1997.

    [12]Weimin Zhang, Ee-Sze Khoo and Tear, T. “A low voltage fully–integrated 0.18um CMOS power amplifier for 5GHz WLAN,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Sept. 2002, pp. 215-218.

    [13]Qiuting Huang, P. Orsatti and F Piazza, “GSM transceiver front-end circuits in 0.25-μm CMOS,” IEEE J. Solid-State Circuits, vol. 34, pp. 292-303, March 1999.

    [14]B. Razavi, “RF Microelectronics,” Prentice Hall PTR, 1998.

    [15]K. A. Bowman, B. L. Austin, J. C. Eble, X. Tang, and J. D. Meindl, “A physical alpha-power law MOSFET model,” IEEE J. Solid-State Circuits, vol. 34, pp. 1410-1414, Oct. 1999.

    [16]T.Sakurai and A. R.Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE J. Solid-State Circuits, vol. 25, pp. 584-594, 1990.

    [17]Yannis P. Tsividis, Operation And Modeling of The MOS Transistor, McGraw-Hill, 1987.

    [18]Trond Ytterdal, Yuhun Cheng, and Tor Fjeldly, Device Modeling for Analog and RE CMOS Circuit Design, John Wiley & Sons Ltd Inc, 2003.

    [19]L. E. Larson, RF and Microwave Circuit Design for Wireless Communication, Artech House, 1996.

    [20]P. J. Sullivan, B. A.Xavier, and W. H.Ku, “Doubly balanced dual-gate CMOS mixer,” IEEE J. Solid-State Circuits, vol. 34, pp. 878-881, 1999.

    [21]R.P. O'Toole, “A 3-V RF-CMOS dual-gate up-conversion mixer,” 1999 IEEE MTT-S Wireless Applications Tech. Symposium Digest, pp. 141-145.

    [22]G. Watanabe, H. Lau, and J. Schoepf, “Integrated mixer design,” in Proc. 2nd IEEE Asia Pacific Conf. ASICs, Aug. 2000, pp. 171-174.

    [23]A. J.Bergsma, A comprehensive design method for dual gate MOSFET mixers, M.Eng. thesis Ottawa, ONT, Canada: Carleton Univ., 1998.

    [24]K. Nimmagadda, G.M. Rebeiz, “A 1.9 GHz double-balanced subharmonic mixer for direct conversion receivers,” 2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers, pp.253-256.

    [25]R. Circa, D. Pienkowski,; S. Jahn, G. Boeck and M. Muller, “Resistive MOSFET mixer for mobile direct conversion receivers,” in Microwave and Optoelectronics Conference, 2003. IMOC 2003. Proceedings of the 2003 SBMO/IEEE MTT-S International, vol. 3, pp. 59-64.

    [26]Hong-Long Wu, Coplanar Waveguide Ka-Band Subharmonic Mixer, NCTU Master Thesis, 2003.

    [27]Jun Wang and A.K.K. Wong, “Effects of mismatch on CMOS double-balanced mixers: a theoretical analysis,” in Proceeding of the 2001 IEEE Electron Devices Meeting, pp.85-88, 2001, Hong Kong.

    [28]L.A. MacEachern, E. Abou-Allam, L. Wang and T. Manku, “Low voltage mixer biasing using monolithic integrated transformer dc-coupling,” in Proceedings of the 1999 IEEE International Circuits and Systems Symposium, vol. 2, pp. 180-183, 1999.

    [29]G. Kathiresan, C. Toumazou, “A low voltage bulk driven downconversion mixer core,” in Proceedings of the 1999 IEEE International Circuits and Systems Symposium, vol. 2, pp. 598-601, 1999.

    [30]Song Ye and Ye Lu, “A 1 V, 1.9 GHz folded dual-gate mixer in CMOS,” in Proceedings of the 2002 3rd International Conference, pp. 175-178, Aug. 2002.

    [31]Moon-Su Yang, Hye-Ryoung Kim and Sang-Gug Lee, “A 900MHz low voltage low power highly linear mixer for direct-conversion receivers,” ICECS 2003, vol. 3, pp. 974-977, Dec. 2003.

    [32]F. Mahmoudi, C.A.T. Salama, “8 GHz, 1 V, high linearity, low power CMOS active mixer,” 2004 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Digest of Papers, pp. 401-404, June 2004.

    [33]P. Gould, C. Zelley and J. Lin, “A CMOS resistive ring mixer MMICs for GSM 900 and DCS 1800 base station applications,” 2000 IEEE MTT-S International Microwave Symposium Digest, vol. 1, pp. 521-524, June 2000.

    [34]T. Melly, A.-S. Porret, C. C. Enz, and E. A. Vittoz, “An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers,” IEEE J. Solid-State Circuits, vol. 36, pp. 102-109, Jan. 2001.

    [35]M. Harada, T. Tsukahara, J. Kodate, A. Yamagishi, and J. Yamada, “2-GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5 V,” IEEE J. Solid-State Circuits, vol. 35, pp. 2000-2004, Dec. 2000.

    [36]T. Manku, G. Beck, and E. Shin, “A low-voltage design technique for RF integrated circuits,” IEEE Trans. Circuits System II, vol. 45, pp. 1408-1413, Nov. 1998.

    [37]Ray-Jay Chiu, The Design of 5.7GHz Power and Low Noise Amplifier and the Research of MMIC Electromagnetic Analysis, NCKU Master Thesis, 2002。

    [38]Chuen-Zhu Guo, 2.4GHz CMOS Linearized Power Amplifier, NCKU Master Thesis, 2003.

    [39]Chen-Kuo Chu, 3.3V Self-Biased 2.4~2.5GHz Power Amplifier MMIC, NCKU Master Thesis, 2003.

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