隨著半導體的演進，CMOS元件不斷微縮以求得更好的效能，但這些奈米尺度的元件卻面臨許多物理極限，多數與短通道效應有關，如：汲極引發位能障下降(DIBL)、熱載子效應等。目前主流解決方法是將元件設計成三維結構，如鰭式電晶體(FinFET)或閘極全環繞式電晶體(Gate All Around FET)，來獲得更佳的閘極控制能力。然而，傳統二維平面結構的完全空乏型絕緣層上矽金氧半場效電晶體(FD-SOI MOSFET)亦是克服短通效應的一個極佳選擇，其在使用未摻雜材料當通道的情況，依舊擁有著優秀的通道控制能力，且比起鰭式電晶體，完全空乏型絕緣層上矽金氧半場效電晶體，有著更簡單的製程技術，以及藉由調整體極電壓或基板摻雜濃度改變門檻電壓的特性。
論文中我們將利用TCAD軟體模擬出的五奈米節點完全空乏型絕緣層上矽金氧半場效電晶體與其特性，在不改變製程技術及元件結構的情況下，將6T-靜態隨機存取記憶體設計為三種不同的組態，比較其讀取的靜態雜訊邊際以及寫入電流。此外，我們也利用EXCEL巨集模擬出靜態隨機存取記憶體在製程上可容忍的誤差，並推算出最小操作電壓。最後，藉由適當的改變體極偏壓，對三種模式下的靜態隨機存取記憶體分別進行優化。此種利用改變體極偏壓優化最小操作電壓的技術可在不使製成變複雜的情況下，令元件的設計更加具有彈性及潛力。

As CMOS technology industry continues to scale, especially at sub 22 nm node, many physical limitations mostly related to short channel effect (SCE), such as drain-induced barrier lowering and hot carrier effect, have surfaced. The mainstream solution is to use 3D structure devices, e.g. FinFET and Gate-All-Around (GAA) FET, to increase the gate controllability. However, we can still use FD-SOI of the 2D planar structure to eliminate SCE because of its excellent electrostatic control of channel with no channel doping required. Compared to FinFET, a simpler process is used in FD-SOI, and we can control its threshold voltage by modifying back bias or changing substrate doping.
This thesis demonstrates a body-biasing 6T-SRAM design technique using 5nm-node mutil-Vt FD-SOI devices, which offers three operation modes: high-performance mode, standard mode and low-voltage mode, without complicated process technology requirements. The read SNM and write current are demonstrated using Synopsys Sentaurus TCAD mixed-mode simulation. We also make use of the technique to optimize Vmin of the 6T-SRAM based on 5nm-node multi-Vt FD-SOI devices. By properly selecting the back bias, the lowest Vmin is achieved for each of the three operation modes: high-performance, standard and low-voltage modes. The proposed technique offers a design flexibility for optimizing the SRAM performance and yield by adjusting the back bias without complicated process technology requirements.

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