在先前的研究[4]中，提出了一個強健的分散式估計機制，此機制適用於存在錯誤節點的感測網路之中，稱為合作式感測節點錯誤偵測機制(collaborative sensor fault detection, CSFD)。此機制可以有效的分偵測感測網路中的錯誤節點並且大大的改善估計的精準度。雖然CSFD的效能很好，但是它在分辨錯誤節點以及估計的過程中需要相當大的計算量，例如對數、乘法以及除法運算…等。在許多即時的無線感測網路的應用中，決策中心需要以特殊應用的積體電路(ASIC)方式來實現，並且整合在一個可單獨運作的裝置中，所以就必須要有一個簡單且有效率的偵錯及估計的方法，此方法又需具備低複雜度的特性以便實作成硬體。所以在此論文中，我們提出了一個具備低複雜度且有效率的方法，稱為有效率的合作式感測節點錯誤偵測機制(Efficient collaborative sensor fault detection, E-CSFD)，我們提出一個簡單的錯誤權重計算方法來取代原本方法，除此之外，為了適合硬體實作也簡化其他式子的運算複雜度。我們使用TSMC 0.18 μm的標準元件庫來實現此電路，E-CSFD電路的邏輯閘數為22589，核心大小為 ，其工作頻率可達167MHz，功率消耗為12.83345 mW。模擬結果指出相較於傳統的方法，E-CSFD在估計的效能上具有較優異的表現。

A robust distributed estimation scheme for fusion center in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research [4]. The scheme can identify the faulty nodes efficiently and improve the accuracy of the estimates significantly. It achieves very good performance at the expense of such extensive computations as logarithm, multiplication and division in the detecting and estimating process. In many real-time WSN applications, the fusion center might be implemented with the ASIC and included in a standalone device. Therefore, a simple and efficient distributed estimation scheme requiring lower hardware cost and power consumption is extremely desired for fusion center. In this paper, we propose the efficient collaborative sensor fault detection (ECSFD) scheme and its VLSI architecture. A simple method for measuring faulty weight is designed. Given the low circuit complexity, it is suitable for hardware implementation. The circuit of E-CSFD contains 22589 gates and requires the core size of by using TSMC 0.18 μm cell library. It can operate at the clock rate of 167 MHz with a power consumption of 12.83345 mW. Simulation results indicate the accuracy of the estimates obtained from the E-CSFD better than that obtained from a conventional approach when applied in sensor networks.

[1] Smart Dust, http://robotics.eecs.berkeley.edu/~pister/SmartDust/
[2] MIT Technology Review, http://www.technologyreview.com
[3] E. Ertin, R. Moses, and L. Potter, “Network parameter estimation with detection failures,” in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., vol. 2, May 2004, pp. 273–276.
[4] T.-Y. Wang, L.-Y. Chang, and P.-Y. Chen, “A Collaborative Sensor-Fault Detection Scheme for Robust Distributed Estimation in Sensor Networks”, IEEE Trans. on Communications, vol. 57, no. 10, pp. 3045–3058, Oct. 2009.
[5] I. F. Akyildiz, W. Su, Y. Sankarasubramaniam, and E. Cayirci, “A survey on sensor networks,” IEEE Communications Magazine, pp. 102–114, August 2002.
[6] W.-M. Lam and A. R. Reibman, “Design of quantizers for decentralized estimation systems,” IEEE Trans. on Communications, vol. 41, no. 11, pp. 1602–1605, November 1993.
[7] J. A. Gubner, “Distributed estimation and quantization,” IEEE Trans. Inform. Theory, vol. 39, no. 4, pp. 1456–1459, July 1993.
[8] V. Megalooikonomou and Y. Yesha, “Quantizer design for distributed estimation with communication constraints and unknown observation statistics,” IEEE Trans. on Communications, vol. 48, no. 2, pp. 181–184, February 2000.
[9] D. Blatt and A. Hero, “Distributed maximum likelihood estimation for sensor networks,” in Proc. IEEE Int. Conf. Acoust., Speech, Signal Process., vol. 3, May 2004, pp. 929–932.
[10] Y. Zhu, E. Song, J. Zhou, and Z. You, “Optimal dimensionality reduction of sensor data in multisensor estimation fusion,” IEEE Trans. Signal Process., vol. 53, no. 5, pp. 1631–1639, May 2005.
[11] Z.-Q. Luo, “An isotropic universal decentralized estimation scheme for a bandwidth constrained ad hoc sensor network,” IEEE Journal of Selected Areas in Communications, vol. 23, no. 4, pp. 735–744, April 2005.
[12] ——, “Universal decentralized estimation in a bandwidth constrained sensor network,” IEEE Trans. Inform. Theory, vol. 51, no. 6, pp. 2210–2219, June 2005.
[13] R. Niu and P. K. Varshney, “Target location estimation in sensor networks with quantized data,” IEEE Trans. on signal processing, vol. 54, no. 12, pp. 4519–4528, December 2006.
[14] A. Ribeiro and G. B. Giannakis, “Bandwidth-constrained distributed estimation for wireless sensor networks– part i: Gaussian case,” IEEE Trans. Signal Processing, vol. 54, no. 7, pp. 2784–2796, July 2006.
[15] ——, “Bandwidth-constrained distributed estimation for wireless sensor networks– part ii: Unknown probability density function,” IEEE Trans. Signal Processing, vol. 54, no. 7, pp. 2784–2796, July 2006.
[16] C. Shen, C. Srisathapornphat, and C. Jaikaeo, “Sensor information networking architecture and applications,” IEEE Personal Communications, vol. 8, no. 4, pp. 52–59, August 2001.
[17] I. Rapoport and Y. Oshman, “A new estimation error lower bound for interruption indicators in systems with uncertain measurements,” IEEE Trans. Inf. Theory, vol. 50, no. 12, pp. 3375–3384, December 2004.
[18] V. Delouille, R. N. Neelamani, and R. G. Baraniuk, “Robust distributed estimation using the embedded subgraphs algorithm,” IEEE Trans. Signal Processing, vol. 54, no. 8, pp. 2998–3010, August 2006.
[19] P. Ishwar, R. Puri, K. Ramchandran, and S. S. Pradhan, “On rateconstrained distributed estimation in unreliable sensor networks,” IEEE Journal of Selected Areas in Communications, vol. 23, no. 4, pp. 765–775, April 2005.
[20] R. C. Elandt-Johnson, Probability Models and Statistical Methods in Genetics. New York, London, Sydney, Toronto: John Wiley &Sons, Inc., 1971.
[21] T. M. Cover and J. A. Thomas, Elements of Information Theory. USA: John Wiley & Sons, Inc., 1991.
[22] R. C. Elandt-Johnson, Probability Models and Statistical Methods in Genetics. New York, London, Sydney, Toronto: John Wiley &Sons, Inc., 1971.
[23] J.-M. Muller, Elementary Functions: Algorithms and Implementation. Birkhauser, 1997.
[24] M.J. Schulte and E.E. Swartzlander Jr., “Hardware Designs for Exactly Rounded Elementary Functions,” IEEE Trans. Computers, vol. 43, no. 8, pp. 964-973, Aug. 1994.
[25] M.J. Schulte and J.E. Stine, “Symmetric Bipartite Tables for Accurate Function Approximation,” Proc. 13th Symp. Computer Arithmetic, pp. 175-183, 1997.
[26] M.J. Arnold and C. Walter, “Unrestricted Faithful Rounding Is Good Enough for Some LNS Applications,” Proc. 15th IEEE Symp. Computer Arithmetic, pp. 237-246, June 2001.
[27] J.N. Mitchell Jr., “Computer Multiplication and Division Using Binary Logarithms,” IRE Trans. Electronic Computers, vol. 11, pp. 512-517, Aug. 1962.
[28] E.L. Hall, D.D. Lynch, and S.J. Dwyer III, “Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications,” IEEE Trans. Computers, vol. 19, pp. 97-105, Feb. 1970.
[29] S. L. SanGregory, C. Brothers, D. Gallagher and R. Siferd, “A Fast, Low-Power Logarithm Approximation with CMOS VLSI Implementation,” Proc. IEEE 42nd Midwest Symp. Circuits and Systems. Vol. 1, pp. 388-391, Aug. 1999.
[30] K. H. Abed and R. E. Siferd, “VLSI Implementation of a Low-Power Antilogarithmic Converter,” IEEE Trans. Computers, Vol. 52, No. 9, pp. 1221–1228, Sept. 2003.
[31] H. Kim, B.G. Nam, J.H. Sohn, and H.J. Yoo, “A 231MHz, 2.18mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3D Graphics System,” in Proc. IEEE J. Solid-State Circuits, Vol. 41, No. 11, pp.2373-2381 Nov. 2006.
[32] S. P. Lloyd, “Least squares quantization in PCM,” IEEE Trans. Inform. Theory, vol. IT-28, pp. 129–136, March 1982.