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研究生: 余仁傑
Yu, Ren-Jie
論文名稱: 應用於 5G 與衛星通訊之毫米波發射端功率放大器與雙刀雙擲開關設計
Design of mmWave TX Front-End Power Amplifiers and a DPDT Switch for 5G and Satellite Communications
指導教授: 王永和
Wang, Yeong-Her
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics Engineering
論文出版年: 2026
畢業學年度: 114
語文別: 英文
論文頁數: 130
中文關鍵詞: 功率放大器併發雙頻功率放大器開關
外文關鍵詞: Power Amplifier, Concurrent dual-band power amplifier, Switch
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  • 本論文第一部分採用WIN 0.12 μm GaN HEMT 製程,實現一款應用於 28 GHz 頻段之功率放大器。電路採用二級放大架構,設計過程中首先利用 load-pull 分析,求得電晶體於目標頻率下之最佳輸出負載阻抗,並以此作為匹配網路之設計基礎。模擬結果顯示,於 28 GHz 操作頻率下,所提出之功率放大器可達到 22.1 dB 的小訊號增益,34.3 dBm 的輸出功率,以及 22% 的最大功率附加效率,實際使用晶片面積為 1.7 × 1.7 mm²。此功率放大器分別採用 on-wafer 與 chip-mounted-on-PCB 兩種方式進行量測。第一次 on-wafer 量測結果顯示,小訊號增益為 19.5 dB,輸出功率為 31.8 dBm,最大功率附加效率為 17.3%。第二次採用 chip-mounted-on-PCB 方式量測時,小訊號增益提升至 21.1 dB、輸出功率達 33.2 dBm,最大功率附加效率為 22.9%。
    第二部分同樣使用WIN 0.12 μm GaN HEMT 製程實現一顆 Ku/Ka 頻段併發雙頻放大器。為同時支援不同頻段操作需求,電路採用上下兩路功率放大器架構,分別對應 Ku 與 Ka 頻段,並經由合波網路完成輸出整合。透過各路徑獨立匹配設計,使電路於兩個頻段下皆能維持良好的增益、輸出功率與穩定性。模擬結果顯示,於 15 GHz 與 28 GHz 操作頻率下,小訊號增益分別為 22 dB 與 19 dB,輸出功率皆大於33 dBm,最大功率附加效率分別23%與19%,實際使用晶片面積為 2.7*1.7 mm²。量測結果顯示,在 15 GHz 和大約 27.4 GHz 時,所製造的 PA 分別實現了 20.5 dB 和 15.2 dB 的測量增益、超過 32 dBm 和 31 dBm 的輸出功率以及 30.8% 和 19.5% 的最大 PAE。
    第三部分使用WIN GaN 0.12 μm HEMT 製程設計雙刀雙擲(DPDT)射頻開關電路。電路採用傳統背對背架構,以形成對稱訊號路徑並改善高頻操作下之隔離與插入損耗表現。藉由適當調整開關元件尺寸與偏壓條件,使開關在目標頻率下兼具良好的傳輸特性與隔離能力。模擬結果顯示,於 21.9~30.9 GHz 操作頻率下,插入損耗約為3.4 - 4 dB,隔離度可達30 dB,回波損耗優於10 dB,實際使用晶片面積為1.2*1.2 mm²。

    The first part of this thesis presents a 28-GHz power amplifier (PA) implemented using the WIN 0.12-μm GaN HEMT process. A two-stage amplifier architecture is adopted. During the design process, load-pull analysis is first performed to determine the optimum load impedance of the transistor at the target frequency, which serves as the basis for the matching-network design. Simulation results show that, at 28 GHz, the proposed PA achieves a small-signal gain of 22.1 dB, an output power of 34.3 dBm, and a maximum PAE of 22%, with core chip area of 1.7 × 1.7 mm². The fabricated PA is characterized using both on-wafer and chip-mounted-on-PCB measurement configurations. The on-wafer measurement results show a small-signal gain of 19.5 dB, an output power of 31.8 dBm, and a maximum PAE of 17.3%. In the chip-mounted-on-PCB measurements, the PA achieves a small-signal gain of 21.1 dB, an output power of 33.2 dBm, and a maximum PAE of 22.9%.
    The second part of this thesis presents a concurrent dual-band power amplifier (PA) operating in the Ku- and Ka-band, implemented using the WIN 0.12-μm GaN HEMT process. To simultaneously support operation at two frequency bands, the proposed circuit adopts a dual-path architecture, in which the upper and lower amplifier paths are designed for the Ka- and Ku-band, respectively. The outputs of the two amplifier paths are combined through an output combining network. By independently optimizing the matching networks for each signal path, the proposed PA achieves satisfactory gain, output power, and stability in both operating bands. Simulation results show that, at 15 GHz and 28 GHz, the proposed PA achieves small-signal gains of 22 dB and 19 dB, output powers exceeding 33 dBm in both bands, and maximum PAEs of 23% and 19%, respectively, with core chip area of 2.7 × 1.7 mm². Measurement results demonstrate that, at 15 GHz and approximately 27.4 GHz, the fabricated PA achieves measured gains of 20.5 dB and 15.2 dB, output powers exceeding 32 dBm and 31 dBm, and maximum PAEs of 30.8% and 19.5%, respectively.
    The third part of this thesis presents a double-pole double-throw (DPDT) RF switch implemented using WIN 0.12-μm GaN HEMT process. The proposed switch adopts a conventional back-to-back topology to provide a symmetrical signal path while improving isolation and insertion loss performance at high frequencies. By appropriately optimizing the dimensions of the switching transistors and the bias conditions, the proposed switch achieves favorable transmission characteristics and high isolation over the target frequency range. Simulation results show that, over the frequency range of 21.9–30.9 GHz, the proposed DPDT switch exhibits an insertion loss of 3.4–4.0 dB, an isolation greater than 30 dB, and a return loss better than 10 dB, with core chip area of 1.2 × 1.2 mm².

    摘要I AbstractIII 致謝V Table of ContentsVII List of FiguresXIII CHAPTER 1Introduction1 1.1Overview 1 1.2Motivation6 1.3Thesis Structure8 CHAPTER 2Fundamentals of Power Amplifiers10 2.1Definitions of Power Amplifiers10 2.2Definitions of Amplifier Parameters 11 2.2.1Output Power11 2.2.2Power Gain11 2.2.3Efficiency12 2.2.41-dB Gain Compression12 2.2.5Stability13 2.2.6Power Amplifier Architectures and Design Trade-Offs14 CHAPTER 3Load Impedance Determination and the PA Design Procedure19 3.1Overview 19 3.1.1Load Line Theory20 3.1.2Load-Pull Measurement21 3.2 Power Amplifier Design Procedure22 CHAPTER 428 GHz 2W GaN-Power Amplifier26 4.1Overview26 4.2Specification26 4.3Ka-band WIN 0.12 μm GaN HEMT Process 2W PA28 4.3.1Circuit Design28 4.3.2Power Stage Device and Bias Selection29 4.3.3Power Stage Load-Pull Analysis31 4.3.4Output Matching Network33 4.3.5Driver Stage Device and Bias Selection36 4.3.6Interstage and Input Matching Network Design37 4.3.7Overall-Circuit Load-Pull Simulation39 4.3.8Layout Diagram and Chip Photograph41 4.3.9Simulation and Measured Result42 4.3.10Comparison Table54 4.3.11Conclusion55 CHAPTER 5Concurrent 15/28 GHz Dual-Band Power Amplifier57 5.1Overview57 5.2Specification60 5.3Concurrent 15/28 GHz Dual-Band Power Amplifier61 5.3.1Circuit Design61 5.3.228 GHz PA Design and Performance62 5.3.315GHz PA Design and Performance65 5.3.4Transformer-Combined Load Design68 5.3.5Concurrent Mode69 5.3.6Performance Comparison Between Single-On and Concurrent-On Operation71 5.3.7Measurement Results74 5.4Discussion80 CHAPTER 6RF Switch Design81 6.1Introduction81 6.2Motivation85 6.3Specification86 6.4Design Flow87 6.5Circuit Design90 6.6Simulation Results93 6.7Comparison Table99 6.8Discussion100 CHAPTER 7Conclusion and Future Work102 7.1Conclusion102 7.2Future Work104 References108

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