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研究生: 范揚旻
Fan, Yang-Min
論文名稱: 金屬摻雜之氧化亞銅電阻式記憶體其特性之研究
A Study of the Effects of Metal Doping in Cuprous Oxide for the Application to Resistive Random Access Memory
指導教授: 彭洞清
Perng, Dung-Ching
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2020
畢業學年度: 108
語文別: 中文
論文頁數: 61
中文關鍵詞: 氧化亞銅電阻式記憶體鈉摻雜銻摻雜
外文關鍵詞: Cu2O, RRAM, doping Na, doping Sb
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  • 本論文將探討金屬元素摻雜於氧化亞銅應用於電阻式記憶體之研究。在一般情況下,摻雜金屬元素,會使得氧化亞銅產生更多缺陷。當金屬元素摻雜於氧化亞銅薄膜時,只要其缺陷的能階差很小,就會在其薄膜以及晶界處產生其它額外的缺陷,這種現象會使得在能隙內產生更多能階。因此,電子可以藉由較小的操作電壓跳躍於不同的缺陷,達到載子傳輸。
    在此項研究中,三種在pH=9條件下電鍍的氧化亞銅作為電阻式記憶體之主動層。分別為無摻雜氧化亞銅、摻雜鈉以及摻雜銻之氧化亞銅。使用三電極沉積系統進行電化學沉積,而Ag/AgCl和Pt分別用作參考電極以及輔助電極,透明導電玻璃ITO基板則用作工作電極。將電鍍儀以定電壓-0.4伏並以水浴法將電解液溫度保持在60°C予以電鍍沉積。使用場發射掃描式電子顯微鏡、X光繞射光譜儀、能量色散光譜儀以及化學分析電子光譜儀(ESCA)分析薄膜材料特性。半導體參數分析儀用於電阻式記憶體電流電壓測量。其中,三者參數在Forming步驟上皆屬於Forming-free。在100次電壓循環操作下,無摻雜氧化亞銅、摻雜鈉之氧化亞銅和摻雜銻之氧化亞銅分別有0.3 ~ 3.2V, 0.2 ~ 2V和0.8 ~ 2.9V的Set電壓區間以及0.8~1.9V, 1.2~1.8V和1.6~2.2V的Reset電壓區間。其高低阻態比(HRS/LRS ratio)無摻雜氧化亞銅、摻雜鈉之氧化亞銅和摻雜銻之氧化亞銅分別有1.0,2.0以及1.6個數量級;記憶體保存力(Endurance)其阻態比值,無摻雜氧化亞銅、摻雜鈉之氧化亞銅和摻雜銻之氧化亞銅分別有1.3,2.0以及1.7個數量級。本實驗數據指出,摻雜鈉之氧化亞銅不但在Set/Reset電壓有最小的區間,且在其耐操度和資料保存力上也有最好的特性。本實驗中的兩個不同金屬摻雜氧化亞銅薄膜確實改善了電阻式記憶體的電性特性。
    沉積氧化亞銅薄膜運用簡易且方便電鍍方式,此方式與CMOS製程過程相容。Forming-free、較低的Set/Reset操作電壓以及功耗較低等優勢,相信優化過後的摻雜鈉之氧化亞銅作為電阻式記憶體於未來記憶體的應用上會有很大的潛力。

    This thesis studies the efforts of metal elements doping in cuprous oxide (Cu2O) for its application to resistive random access memory (RRAM). Doping, in general, can result in more defects in cuprous oxide. When metal is doped into a cuprous oxide thin film, additional defects in the film as well as at grains’ boundaries will be generated, which could generate many energy levels within the forbidden bandgap, as long as the energy level difference of the defects is small enough, the electrons can easily transport via hopping the different defect sites with the help of a small bias voltage.
    In this study, three types of cuprous oxide electroplated at a condition of pH=9 were used as the RRAM active layer. Three types of precursor solutions were prepared for undoped Cu2O (Un-Cu2O), Na-doped Cu2O (Cu2O_Na) and Sb-doped Cu2O (Cu2O_Sb). Electrodeposition was carried out by using three-electrode electrodeposition system, whereas Ag/AgCl and Pt were used as a reference electrode and a counter electrode respectively. The ITO substrate was used as a working electrode. The deposition was potentiostatically controlled at a voltage of -0.4V, and the electrolyte temperature during the deposition process was maintained at 60°C using a water bath. The deposited film properties were analyzed using scanning electron microscope, X-ray diffractor, energy dispersive spectometer, and X-ray photoelectron spectroscopy. Semiconductor device parameter analyzer was used for RRAM’s current-voltage measurements.
    All three RRAMs have the characteristic of forming free. The range of set voltages, evaluated 100 cycles, of the Un-Cu2O, Cu2O_Na and Cu2O¬_Sb RRAMs are 0.3~3.2V, 0.2~2V and 0.8~2.9V, respectively. The ranges of the reset voltages of the Un-Cu2O, Cu2O_Na and Cu2O¬_Sb RRAM are 0.8~1.9V, 1.2~1.8V and 1.6~2.2V, respectively. The high and low resistance ratio (HRS/LRS) of the Un-Cu2O, Cu2O_Na and Cu2O¬_Sb are about 1.0, 2.0 and 1.6 orders of magnitude, respectively. The high and low resistance ratio in retention of the Un-Cu2O, Cu2O_Na and Cu2O¬_Sb are about 1.1, 2.0 and 1.3 orders of magnitude, respectively. The data indicates that the Cu2O_Na RRAM exhibits not only the smallest set and reset voltages range, but also has better performance in endurance and retention. The two different metal doped Cu2O films do improve the electrical properties and performance of the RRAM devices.
    Electroplating of Cu2O film is a simple process and compatible with CMOS manufacturing process. Forming free and lower set/rest voltages consume low power in RRAM operations. It is believed that an optimized Na doped Cu2O film has the potential to be used in the future for RRAM applications.

    中文摘要 II SUMMARY IV 目錄 VI 表目錄 VIII 圖目錄 IX 第一章 緒論 1 1-1 記憶體簡介 1 1-2 電阻式記憶體 2 1-3氧化亞銅(Cuprous Oxide)特性[14] 3 1-4研究動機 4 第二章 基礎理論 5 2-1元件基礎理論 5 2-2 傳導機制 6 2-2-1 蕭基特發射(Schottky Emission) [22] 7 2-2-2 穿隧(Tunneling) [23] 8 2-2-3 歐姆傳導(Ohmic Conduction) 9 2-2-4 空間電荷限制電流(SCLC)[24] 10 2-2-5 法蘭克-普爾發射(Frenkel-Poole Emission)[25] 11 2-2-6 跳躍傳導(Hopping Conduction)[26][27] 12 第三章 實驗方法 13 3-1 實驗流程圖 13 3-2 實驗材料 14 3-3 前導溶液調配 15 3-3-1 調配氧化亞銅(Un-Cu2O)電鍍液與電化學沉積 15 3-3-2 調配氧化亞銅摻鈉(Cu2O_Na)電鍍液與電化學沉積[20] 15 3-3-3 調配氧化亞銅摻銻(Cu2O_Sb)電鍍液與電化學沉積 16 3-4 基板ITO清洗 17 3-5 電化學沉積(Electrical chemical deposition;ECD)[15] 18 3-6 儀器介紹 19 3-7 製程設備介紹 20 3-7-1 電磁攪拌器 20 3-7-2 電化學沉積儀器 21 3-7-3 濺鍍機 23 3-8 材料分析設備介紹 24 3-8-1 X光繞射光譜儀 24 3-8-2 場發射掃描式電子顯微鏡(FE-SEM) 26 3-8-3 化學分析電子光譜儀(ESCA) 27 3-9 電性分析儀器 28 3-9-1 半導體參數分析儀(B1500) 28 第四章 結果與討論 29 4-1 氧化亞銅電阻式記憶體 29 4-2 材料分析 30 4-2-1 氧化亞銅X光繞射光譜儀分析 31 4-2-2 氧化亞銅SEM材料分析 33 4-2-3 氧化亞銅X射線光電子光譜(XPS)與X射線光譜(EDS)分析 35 4-3電阻式記憶體電性分析 38 4-3-1 I-V曲線圖 39 4-3-2 耐久度(Endurance) 43 4-3-3記憶保存力(Retention) 46 4-3-4 電壓累積分布圖(Voltage Cumulative probability) 49 4-4 機制探討 52 第五章 結論 57 參考文獻 58

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