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研究生: 蔡峻瑋
Tsai, Chun-Wei
論文名稱: 操作於低溫環境之鍺鰭式電晶體的元件特性探討與實現低功耗靜態隨機存取記憶體之研究
Study of device characteristics of germanium FinFETs operating in low temperature and the implementation of low power consumption static random access memory
指導教授: 江孟學
Chiang, Meng-Hsueh
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年: 2022
畢業學年度: 110
語文別: 英文
論文頁數: 73
中文關鍵詞: 鰭式場效電晶體6T-SRAM低溫元件延遲TCAD
外文關鍵詞: FinFETs, TCAD, germanium, low temperature, device delay, 6T-SRAM
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  • 在現今人工智能及物聯網蓬勃的發展下,對於高效能運算的需求日漸提高。為了提高高效能運算晶片的計算性能,降低功耗是一個重要問題。由於高電洞遷移率和較低的能帶隙,以鍺為基底的元件被認為是高效能運算及低功率電路的良好材料。透過低溫元件的概念,可降低操作電壓至0.25V以降低電路的功率。低溫操作環境可以為晶體管提供許多優勢,例如改善亞閾值擺幅 (SS)、降低靜態/動態功率和減少洩漏電流,降低金屬線的電阻,從而降低功耗並提高計算性能。
    此篇論文中,我們利用TCAD模擬可看到低溫所帶來的低功耗優勢,但同時由於電流值的下降,我們的元件延遲隨操作電壓下降而上升。因此,我們改變的元件的尺寸及製程,探討元件延遲與元件尺寸與製程的關係,在不改變操作電壓的前提下降低電路延遲。最後套用可改善元件延遲的製程,成功接成反向器,證明可有效改善邏輯閘延遲;並在最後實現操作於0.25V的低功耗靜態隨機存取記憶體。

    With the rapid development of artificial intelligence (AI) and the Internet of Things (IoT), the demand for high-performance computing is increasing day by day. In order to improve the computing performance of high-performance computing chips, reducing power consumption is an important issue. Due to high hole mobility and low energy bandgap, germanium-based devices are considered to be good materials for high-performance computing and low-power circuits. Through the concept of low-temperature devices, the operating voltage can be reduced to 0.25V to reduce the power of the circuit. A low temperature operating environment can provide transistors with many advantages, such as improved sub-threshold swing (SS), lower static/dynamic power and less leakage current, and lower metal line resistance, resulting in lower power consumption and higher computing performance.
    In this paper, we use TCAD simulations, and use the 2022 version of the 3 nm technology node provided by the International Roadmap for Devices and Systems (IRDS) as a benchmark and then observe the low power benefits of low temperature. At the same time, the device delays increase with lower operating voltages due to lower current values. Therefore, we changed the size and process of the devices, discussed the relationship between device delay and process, and reduced the circuit delay without changing the operating voltage. Finally, a process that can improve the delay of the devices is applied, and the inverter is successfully connected, which proves that it can effectively improve the delay of the logic gate; and realize the low-power static random access memory operates at 0.25V.

    摘要 I Abstract II Contents VI Table Captions VIII Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 3 1.3 Introduction of Simulation Tools 4 1.4 Overview of the Thesis 5 Chapter 2 6 2.1 Germanium 6 2.2 FinFETs Structure 9 2.3 Bulk and GeOI FinFETs 12 2.4 Key Low-Temperature Phenomenon in CMOS Devices 13 2.4.1 Fermi-Dirac Statistics 13 2.4.2 Source to Drain Tunneling 15 2.4.3 Band tail 16 Chapter 3 Device Design and Simulation 18 3.1 Device Design 18 3.2 Model Used in the Device Simulation 21 3.2.1 Temperature Model 21 3.2.2 Fermi-Dirac Statistics 21 3.2.3 Effective Intrinsic Model 21 3.2.4 Mobility Model 22 3.2.5 Generation-Recombination Model 27 3.2.6 Band tail 28 3.2.7 Non-Local Barrier Tunneling 29 3.3 Device Performance at Low Temperature 31 3.3.1 DC characteristics of low temperature GeOI FinFETs 31 3.3.2 SS saturation of low temperature GeOI FinFETs 34 3.4 Impact of Device Delay 36 3.4.1 Effects of the Fin Height 37 3.4.2 Effects of the Fin Width 41 3.4.3 Effects of source/drain concentration 45 3.4.4 Effects of spacer width 49 3.4.5 Effects of Bulk FinFETs and GeOI FinFETs 53 3.4.6 Summary of device delay 57 Chapter 4 Implementation of Low Power Inverter and 6T-SRAM 58 4.1 Implementation of Low Power Inverter 58 4.2 Implementation of Low Power 6T-SRAM 62 Chapter 5 Conclusion 69 References 71

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