在半導體製程中,提昇晶圓製造良率,是降低生產成本的首要課題,也是評量晶圓製造廠優劣的重要指標之一。量產產品的良率,常常因晶圓製造過程中肇因於各種塵埃,化學溶劑,光罩缺陷,..等產生的缺陷而下降。尤其是奈米製程的良率受害更大。在微米或次微米製程技術的中,有些缺陷或許不會造成晶片失效,但當製程技術進入到奈米製程,這些非常細小的defects(或 particles),卻往往成為奈米製程晶片的頭號殺手!
在晶圓製造過程中, 以往用來提昇良率的一貫流程是利用線上缺陷檢驗系統(in-line defect inspection system)來即時偵測缺陷產生的狀況。並當晶圓製作完成,用晶圓測試機台來測試該晶圓上之晶片,以得知每個晶片的良劣及收集詳細測試資料。然後根據這些測試資料,將失效的晶片作失敗性分析(Failure Analysis)來找出造成晶片失效的缺陷,進而提供生產製造流程的改善依據。
但是,失敗性分析既耗費時日又佔用了昂貴的儀器設備資源，而且有時甚至無法真正找出缺陷。尤其當遇到緊急的良率驟降的問題，上述之流程,更無法及時有效地提供Fab 改善製程的依據。如此有可能使晶圓製造良率出現連續性的問題。須停用某一些製造機台,嚴重者甚或必須停止生產線以等待失敗性分析的結果以做為判斷或改善的依據進如此讓工廠遭遇慘重的損失。因此吾人發展一種新穎的比對系統既可降低PFA(Physical Failure Analysis)成本及加速良率改善。
本論文針對這種新穎的比對系統的發展作詳細的說明，並藉由一個晶圓代工廠的FPGA(Field Programmable Gate Array) 90奈米晶片生產線測試數據輸入這個系統來證明這個系統的可用性。首先吾人簡介缺陷密度模式與良率之關係,以解釋為何目前晶圓代工業界均採用缺陷密度以取代良率作為衡量標準。並介紹線上缺陷檢驗及晶圓測試機制。這兩個機制原本各自獨立運作以確保產品品質。我們利用既有線上缺陷檢驗系統資料庫所儲存之缺陷資料,加上與晶圓測試資料作比對。如此,將可在晶圓測試完成後立即得知造成晶片失效的缺陷及原因 ,大幅省卻失敗性分析的人力與儀器機台資源並且大幅改進良率提升的時效及新產品或技術的學習曲線!

As the wafer manufacturing technology scales down to nano-meter regime, the wafer process caused tiny defects occur often. In addition, the effectively killing dimension of defects is also shrunk. Thus, the in-line defect inspection executed in the wafer manufacturing for every process and layers becomes very important. On the other hand, after finish of wafer processing, there also has a wafer testing stage. Both of the inspection and test control the quality and scrapping inside a Fab independently.
Usually, after wafer testing, one starts the PFA (Physical Failure Analysis) by performing the TEM/SEM/FIB (Transmission Electron Microscope/Scanning Electron Microscope/Focused Ion Beam) in the failure chips to have a clear picture of the defects in these failure chips. The testing data provides us the valuable information to localize the defects and the layers which defects occurred. However, it also takes time and occupies the FA equipments resource, thus, impacting the manufacturing significantly. Especially, in case of solving an urgent event and/or serious yield problem, one needs the defect data and root causes immediately. Therefore, one needs a better solution with low cost and high efficiency for shortening the cycle time to improve the yield.
In this thesis, we develop a methodology for the fast yield improvement and evidence its availability with a foundry’s real production line data. Firstly, the developed methodology needs to setup and align the chip information of the GDS coordination system, the reference point or alignment marks, data format and so on. In addition, for the wafer testing raw data handling, it also requires the simple scripts to convert and translate to the topological and then physical locations. Then, compares and matches the data between the in-line defect inspection and wafer testing to find the real killer defect images without extra PFA.

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