在本論文中，我們探討了不同結構與操作電壓的高壓橫向擴散金氧半電晶體(LDMOS)因熱載子所造成元件特性退化的現象與機制。
首先，對於採用0.25微米製程之n型LDMOS電晶體，其熱載子所造成的退化被發現與閘極電流大小有關。根據實驗數據及電腦輔助模擬顯示，在通道區域中由於熱電子注入所造成的介面能態(interface state)被確認為主要的退化機制。因為閘極電流主要是由電子注入所組成，因此，愈大的閘極電流意味著愈嚴重的電子注入。而愈嚴重的電子注入就會造成更多的介面能態，因而產生愈大的元件退化。因此，閘極電流與元件的熱載子壽命時間(lifetime)呈現良好的關連性。最後，我們也評估改變元件設計參數對於元件性能與壽命時間的影響。改變通道長度或N-漂移區邊緣至閘極邊緣的長度對於元件的導通電阻(Ron)壽命時間之改善有較大的影響，而改變閘極邊緣到汲極的長度則影響較小。這樣的分析對於同時考慮元件性能與熱載子可靠度來設計LDMOS電晶體提供了有用的訊息。
將飄移區採用淺槽隔離(STI)之0.25微米製程n型LDMOS電晶體偏壓在中等及高的閘極電壓下，沒有預期到的導通電阻降低之現象被觀察到。當元件操作在中等閘極偏壓下，導通電阻持續的降低一段時間，之後，再轉變為增加的趨勢。當元件操作在高的閘極偏壓下，導通電阻只在stress一開始降低，但之後都隨時間增加而變大。我們提出了造成導通電阻異常偏移的物理機制，並藉由實驗數據及模擬結果得到驗證。當元件偏壓在中等閘極電壓下，熱電洞(hot-hole)注入與捕捉發生在靠近通道區域的STI邊緣，導致了電阻的降低。由熱電洞注入所形成的介面能態則發生在靠近通道區域的STI邊緣及鄰近的漂移區介面，導致了電阻的上升。當元件偏壓在高的閘極電壓下，電洞捕捉也發生在靠近通道區域的STI角落，導致了電阻的降低。由熱電子注入所形成的介面能態則存在靠近汲極的STI邊緣，而這些介面能態主導了導通電阻的特性而立即導致導通電阻的上升。根據提出來的導通電阻退化機制，我們呈現了一個導通電阻的退化模型，並藉由實驗數據獲得驗證。
在最後的部份，針對0.35微米製程之p型LDMOS電晶體其熱載子所造成的臨界電壓(VT)偏移進行探討。當元件操作在閘極偏壓小於汲極偏壓下，臨界電壓有兩種不同的趨勢。在小閘極偏壓條件下，電子被注入並被捕捉在靠近汲極端的通道部分，造成了通道縮減效應。因此臨界電壓些微的上升而線性區汲極電流(Idlin)變大。然而，在大閘極偏壓條件下，臨界電壓嚴重的降低且線性區汲極電流變小。實驗結果顯示，在通道區域中由於熱電洞注入所造成的施體型(donor-type)介面能態是主要造成顯著臨界電壓偏移的因素。最後，這個p型LDMOS電晶體的基極電流(Isub)大小被發現是一個判斷臨界電壓偏移嚴重與否的良好指標。

In this dissertation, hot-carrier-induced degradation and mechanisms in high-voltage lateral diffused metal-oxide-semiconductor (LDMOS) transistors with different structures and operation voltages are investigated.
For the 0.25 μm n-type LDMOS transistors, the hot-carrier-induced degradation is found to be dependent on the magnitude of gate current (Ig). Based on the experimental data and technology computer-aided design (TCAD) simulations, interface state generation (Nit) caused by hot-electron injection in the channel region is identified to be the main degradation mechanism. Since Ig consists mainly of the electron injection, larger Ig means severer electron injection, which would lead to more Nit and hence greater device degradation. As a result, Ig correlates well with the hot-carrier lifetime of the device. Finally, the impact of varying device layout parameter on performance and lifetime are also evaluated. Varying the length of channel (L) or the length from N- drift region edge to poly-gate edge (b) have greater effect on Ron lifetime improvement while varying the length from poly-gate edge to the drain (s) has less effect. The analysis can provide useful information in designing LDMOS devices when considering both device performance and hot-carrier reliability.
Unexpected on-resistance (Ron) decrease under medium and high gate voltage (Vgs) stress conditions is observed in 0.25 μm n-type LDMOS transistors with shallow trench isolation (STI) in the drift region. Under medium stress Vgs, Ron decreases monotonously for a period of time and the tendency turn around later. For the device stressed under high Vgs, Ron decreases at the beginning of stress but increases afterwards as the stress time increases. The mechanisms responsible for anomalous Ron shift are proposed and verified with experimental data and TCAD simulations. When the device is stressed under medium Vgs, hot-hole injection and trapping occurs at the STI edge closest to the channel, resulting in Ron reduction. Nit caused by hot-hole injection occurs at the STI edge closest to the channel and nearby drift region, leading to Ron increase. For the device stressed under high Vgs, hole trapping at the STI corner closest to the channel takes place, causing Ron reduction. Nit created by hot-electron injection at the STI edge closest to the drain dominates Ron characteristics and leads to Ron increase immediately. Based on the proposed Ron degradation mechanisms, a Ron degradation model is discussed and verified with experimental data.
In the final part, hot-carrier-induced threshold voltage (VT) shift in the 0.35μm p-type LDMOS transistors is investigated. Two opposite tendencies are observed in VT under bias condition of |Vgs| < |Vds|, and the responsible degradation mechanisms are presented. At low Vgs bias condition, electrons are injected and trapped in the channel near the drain, resulting in channel reduction. Therefore, VT increases slightly and linear drain current (Idlin) increases. At high Vgs bias condition, however, severe VT decrease with Idlin decrease are found after stress. Experimental results indicate that donor-type interface traps created by hole injection in the channel region is the dominant factor for significant VT shift. Finally, the magnitude of Isub is found to be a good monitor to judge the severity of VT shift in this pLDMOS device.

[1] B. J. Baliga, “Trends in Power Semiconductor Devices,” IEEE Trans. Electron Devices, vol. 43, no. 10, pp. 1717-1731, 1996.
[2] P. Hower, “Safe operating area—a new frontier in LDMOS design,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 1-8, 2002.
[3] K. M. Wu, “Development and hot-carrier reliability study of integrated high-voltage MOSFET Transistors,” dissertation for Doctor of Philosophy at Nation Cheng Kung University, 2007.
[4] C. Y. Tsai, T. Efland, S. Pendharkar, J. Mitros, A. Tessmer, J. Smith, J. Erdeljac, and L. Hutter, “16–60 V rated LDMOS show advanced performance in an 0.72 μm evolution BiCMOS power technology,” in IEDM Tech. Dig., pp. 367-370, 1997.
[5] V. Parthasarathy, R. Zhu, W. Peterson, M. Zunino, and R. Baird, “A 33 V, 0.25 mΩ*cm2 n-channel LDMOS in a 0.65 μm smart-power technology for 20-30 V operation,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 61-64, 1998.
[6] J. A. van der Pol, A. W. Ludikhuize, H. G. A. Huizing, B. van Velzen, R. J. E. Hueting, J. F. Mom, G. van Lijnschoten, G. J. J. Hessels, E. F. Hooghoudt, R. van Huizen, M. J. Swanenberg, J. H. H. A. Egbers, F. van den Elshout, J. J. Koning, H. Schligtenhorst, and J. Soeteman, “A-BCD: An economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 327-330, 2000.
[7] T. Terashima, F. Yamamoto, and K. Hatasako, “Multi-voltage device integration technique for 0.5μm BiCMOS and DMOS process,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 331-334, 2000.
[8] Y. Kawagushi, K. Nakamura, K. Karouji, K. Watanabe, Y. Yamaguchi, and A. Nakagawa, “0.6 μm BiCMOS-based 15 and 25 V LDMOS for analog applications,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 169-172, 2001.
[9] P. Moens, D. Bolognesi, L. Delobel, D. Villanueva, H. Hakim, S. C. Trinh, K. Reynders, F. De Pestel, A. Lowe, E. De Backer, G. Van Herzeele, and M. Tack, “I3T80: A 0.35 μm based system-on-chip technology for 42 V battery automotive applications,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 225-228, 2002.
[10] A. G. Sabnis, “VLSI reliability,” in VLSI Electronic Microstructure Science, vol. 22, Academic Press, New York, Chapter 6, 1990.
[11] C. Y. Chang and S. M. Sze, “ULSI Technology,” McGraw-Hill, New York, pp. 657-658, 1996.
[12] R. Versari, A. Pieracci, S. Manzini, C. Contiero, and B. Ricco, “Hot-carrier reliability in submicrometer LDMOS transistors,” in IEDM Tech. Dig., pp. 371-374, 1997.
[13] S. Manzini, A. Gallerano, and C. Contiero, “Hot-electron injection and trapping in the gate oxide of submicron DMOS transistors,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 415-418, 1998.
[14] R. Versari and A. Pieracci, “Experimental study of hot-carrier effects in LDMOS transistors,” IEEE Trans. Electron Devices, vol. 46, no. 6, pp. 1228-1233, 1999.
[15] P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, “A novel hot hole injection degradation model for lateral DMOS transistors,” in IEDM Tech. Dig., pp. 877-880, 2001.
[16] P. Moens, G. Van den bosch, G. Groeseneken, and D. Bolognesi, “A unified hot carrier degradation model for integrated lateral and vertical nDMOS transistors,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 88-91, 2003.
[17] P. Moens, G. Van den bosch, and G. Groeseneken, “Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors,” in Proc. Int. Reliability Physics Symp., pp. 214-221, 2003.
[18] T. Nigam, A. Shibib, S. Xu, H. Safar, and L. Steinberg, “Nature and location of interface traps in RF LDMOS due to hot carriers,” Microelectron. Eng., vol. 72, no. 1-4, pp. 71-75, 2004.
[19] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. De Keersmaecker, “A reliable approach to charge pumping measurements in MOS-transistors,” IEEE Trans. Electron Devices, vol. 31, no. 1, pp. 42-53, 1984.
[20] P. Heremans, J. Witters, G. Groeseneken, and H. E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degraation,” IEEE Trans. Electron Devices, vol. 36, no. 7, pp. 1318-1335, 1989.
[21] A. B. M. Elliot, “The use of charge pumping currents to measure surface state densities in MOS-transistors” Solid-State Electron., vol. 19, no. 3, pp. 241-247, 1976.
[22] S. Manzini and C. Contiero, “Hot-electron-induced degradation in high-voltage submicron DMOS transistors,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 65-68, 1996.
[23] V. O’Donovan, S. Whiston, A. Deignan, and C. N. Chleirigh, “Hot carrier reliability of lateral DMOS transistors,” in Proc. Int. Reliability Physics Symp., pp. 174-179, 2000.
[24] P. Moens, M. Tack, R. Degraeve, and G. Groeseneken, “A novel hot-hole injection degradation model for lateral nDMOS transistors,” in IEDM Tech. Dig., pp. 877-880, 2001.
[25] D. Brisbin, A. Strachan, and P. Chaparala, “Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications,” in Proc. Int. Reliability Physics Symp., pp. 105-110, 2002.
[26] P. Moens, G. Van den bosch, C. De Keukeleire, R. Degraeve, M. Tack, and G. Groeseneken, “Hot hole degradation effects in lateral nDMOS transistors,” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1704-1710, 2004.
[27] P. L. Hower and S. Pendharkar, “Short and long-term safe operating area consideration in LDMOS transistors,” in Proc. Int. Reliability Physics Symp., pp. 545-550, 2005.
[28] J. F. Chen, K. M. Wu, K. W. Lin, Y. K. Su, and S. L. Hsu, “Hot-carrier reliability in submicrometer 40V LDMOS transistors with thick gate oxide,” in Proc. Int. Reliability Physics Symp., pp. 560-564, 2005.
[29] C. Hu, S. C. Tam, F. C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, “Hot-electron-induced MOSFET degradation—Model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 375-385, 1985.
[30] K. M. Wu, J. F. Chen, Y. K. Su, J. R. Lee, Y. C. Lin, S. L. Hsu, and J. R. Shih, “Anomalous reduction of hot-carrier-induced ON-resistance degradation in n-type DEMOS transistors,” IEEE Trans. Device Mater. Reliab., vol. 6, no. 3, pp. 371-376, 2006.
[31] S. Tam, P. Ko, and C. Hu, “Lucky-electron model of channel hot-electron injection in MOSFETs,” IEEE Trans. Electron Devices, vol. 31, no. 9, pp. 1116-1125, 1984.
[32] E. Takeda, A. Shimizu, and T. Hagiwara, “Role of hot-hole injection in hot-carrier effects and the small degraded channel region in MOSFET’s,” IEEE Electron Device Lett. vol. 4, no. 9, pp. 329-331, 1983.
[33] C. Hu, “Hot-electron effects in MOSFETs,” in IEDM Tech. Dig., pp. 176-181, 1983.
[34] K. R. Hoffmann, W. Weber, C. Werner, and G. Dorda, “Hot-electron and hole emission effects in short n-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 32, no. 3, pp. 691-699, 1985.
[35] Y. Q. Li, C. A. T. Salama, M. Seufert, and M. King, “Submicron BiCMOS compatible high-voltage MOS transistors,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 355-358, 1994.
[36] S. Whiston, D. Bain, A. Deignan, J. Pollard, C. N. Chleirigh, and C. M. M. O’Neill, “Complementary LDMOS transistors for a CMOS/BiCMOS process,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 51-54, 2000.
[37] Y. Q. Li, C. A. T. Salama, M. Seufert, P. Schvan, and M. King, “Design and characterization of submicron BiCMOS compatible high-voltage NMOS and PMOS devices,” IEEE Trans. Electron Devices, vol. 44, no. 2, pp. 331-338, 1997.
[38] S. Pendharkar, T. Efland, and C. Y. Tsai, “Analysis of high current breakdown and UIS behavior of resurf LDMOS (RLDMOS) devices,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 419-422, 1998.
[39] J. F. Chen, K. S. Tian, S. Y. Chen, J. R. Lee, K. M. Wu, and C. M. Liu, “Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide-semiconductor transistors,” Appl. Phys. Lett., vol. 92, no. 24, p. 243501, 2008.
[40] J. F. Chen, J. R. Lee, K. M. Wu, T. Y. Huang, and C. M. Liu, “Effect of drift-region concentration on hot-carrier-induced Ron degradation in nLDMOS transistors,” IEEE Electron Devices Lett., vol. 29, no. 7, pp. 771-774, 2008.
[41] D. G. Lin, S. L. Yu, Y. C. See, and P. Tam, “A novel LDMOS structure with a step gate oxide,” in IEDM Tech. Dig., pp. 963-966, 1995.
[42] A. Nezar and C. A. T. Salama, “Breakdown voltage in LDMOS transistor using internal field rings,” IEEE Trans. Electron Devices, vol. 38, no. 7, pp. 1676-1680, 1991.
[43] T. Efland, P. Mei, D. Mosher, and B. Todd, “Self-aligned RESURF to LOCOS region LDMOS characterization shows excellent Rsp vs BV performance,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 147-150, 1996.
[44] M. Zitouni, F. Morancho, H. Tranduc, P. Rossel, J. Buxo, I. Pages, and S. Merchant, “A new lateral power MOSFET for smart power ICs: the LUDMOS concept,” Microelectron. J., vol. 30, no. 6, pp. 551-561, 1999.
[45] E. de Fresart, R. De Souza, J. Morrison, P. Parris, J. Heddleson, V. Venkatesan, W. Paulson, D. Collins, G. Nivison, B. Baumert, W. Cowden, and D. Blomberg, “Integration of multi-voltage analog and power devices in a 0.25µm CMOS + flash memory process,” in Proc. Int. Symp. Power Semiconductor Devices and ICs, pp. 305-308, 2002.
[46] B. Wang, H. Nguyen, J. Mavoori, A. Horch, Y. Ma, T. Humes, and R. Paulsen, “Effect of layout orientation on the performance and reliability of high voltage N-LDMOS in standard submicron logic STI CMOS process,” in Proc. Int. Reliability Physics Symp., pp. 654-655, 2005.
[47] X. Han and C. Xu, “Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology,” Microelectron. J., vol. 38, no. 10-11, pp. 1038-1041, 2007.
[48] Y. Rey-Tauriac, J. Badoc, B. Reynard, R. A. Bianchi, D. Lachenal, and A. Bravaix, “Hot-carrier reliability of 20V MOS transistors in 0.13 μm CMOS technology,” Microelectron. Reliab., vol. 45, no. 9-11, pp. 1349-1354, 2005.
[49] K. M. Wu, J. F. Chen, Y. K. Su, J. R. Lee, K. W. Lin, J. R. Shih, and S. L. Hsu, “Effect of gate bias on hot-carrier reliability in drain extended metal-oxide-semiconductor transistors,” Appl. Phys. Lett., vol. 89, no. 18, p. 183522, 2006.
[50] P. Moens and G. Van den bosch, “Characterization of total safe operating area of lateral DMOS transistors,” IEEE Trans. Device Mater. Rel., vol. 6, no. 3, pp. 349-357, 2006.
[51] D. Brisbin, P. Lindorfer, and P. Chaparala, “Substrate current independent hot carrier degradation in NLDMOS devices,” in Proc. Int. Reliability Physics Symp., pp. 329-333, 2006.
[52] P. Moens, J. Mertens, F. Bauwens, P. Joris, W. De Ceuninck, and M. Tack, “A comprehensive model for hot carrier degradation in LDMOS transistors,” in Proc. Int. Reliability Physics Symp., pp. 492-497, 2007.
[53] D. Varghese, S. Mahapatra, and M. A. Alam, “Hole energy dependent interface trap generation in MOSFET Si/SiO2 interface,” IEEE Electron Device Lett., vol. 26, no. 8, pp. 572-574, 2005.
[54] S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, “A comprehensive framework for predictive modeling of negative bias temperature instability,” in Proc. Int. Reliability Physics Symp., pp. 273-282, 2004.
[55] J. D. Bude, B. E. Weir, and P. J. Silverman, “Explanation of stress-induced damage in thin oxides,” in IEDM Tech. Dig., pp. 179-182, 1998.
[56] B. S. Doyle, J. C. Marchetaux, M. Bourcerie, and A. Boudou, “The effect of substrate bias on hot-carrier damage in NMOS devices,” IEEE Electron Device Lett., vol. 10, no. 1, pp. 11-13, 1989.
[57] B. S. Doyle, M. Bourcerie, J. C. Marchetaux, and A. Boudou, “Interface state creation and charge trapping in the medium-to-high gate voltage range (Vd/2  Vg  Vd) during hot carrier stressing of n-MOS transistors,” IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 744-755, 1990.
[58] J. M. Aitken and D. R. Young, “Avalanche injection of holes into SiO2,” IEEE Trans. Nucl. Sci., vol. 24, no. 6, pp. 2128-2134, 1977.
[59] T. Tsuchiya and J. Frey, “Relationship between hot-electrons/holes and degradation of p- and n-channel MOSFET’s,” IEEE Electron Dev. Lett., vol. 6, no. 1, pp. 8-11, 1985.
[60] M. Koyanagi, A. G. Lewis, J. Zhu, R. A. Martin, T. Y. Huang, and J. Y. Chen, “Investigation and reduction of hot electron induced punchthrough (HEIP) effect in submicron PMOSFETs,” in IEDM Tech. Dig., pp. 722-725, 1986.
[61] Y. Hiruta, K. Maeguchi, and K. Kanzaki, “Impact of hot electron trapping on half micron PMOSFETS with p+ poly Si gate,” in IEDM Tech. Dig., pp. 718-721, 1986.
[62] F. Matsuoka, H. Hayashida, K. Hama, Y. Toyoshima, H. Iwai, and K. Maeguchi, “Drain avalanche hot hole injection mode on PMOSFETs,” in IEDM Tech. Dig., pp. 18-21, 1988.
[63] Q. Wang, M. Brox, W. H. Kraustschneider, and W. Weber, “Explanation and model for the logarithmic time dependence of p-MOSFET degradation,” IEEE Electron Dev. Lett., vol. 12, no. 5, pp. 218-220, 1991.
[64] T. C. Ong, P. K. Ko, and C. Hu, “Hot-carrier current modeling and device degradation in surface-channel p-MOSFET’s,” IEEE Trans. Electron Dev., vol. 37, no. 7, pp. 1658-1666, 1990.
[65] T. Tsuchiya, Y. Okazaki, M. Miyake, and T. Kobayashi, “New hot-carrier degradation mode and lifetime prediction method in quarter-micrometer PMOSFET,” IEEE Trans. Electron Dev., vol. 39, no. 2, pp. 404-408, 1992.
[66] S. Aresu, W. De Ceuninck, G. Van den bosch, G. Groeseneken, P. Moens, J. Manca, D. Wojciechowski, and P. Gassot, “Evidence for source side injection hot carrier effects on lateral DMOS transistors,” Microelectron. Reliab., vol. 44, pp. 1621-1624, 2004.
[67] D. Brisbin, A. Strachan, and P. Chaparala, “Optimizing the hot carrier reliability of N-LDMOS transistor arrays,” Microelectron. Reliab., vol. 45, pp. 1021-1032, 2005.
[68] J. R. Lee, J. F. Chen, K. M. Wu, C. M. Liu, and S. L. Hsu, “Effect of hot-carrier-induced interface states distribution on linear drain current degradation in 0.35 µm n-type lateral diffused metal-oxide-semiconductor transistors,” Appl. Phys. Lett., vol. 92, no. 10, p. 103510, 2008.
[69] S. Y. Chen, J. F. Chen, J. R. Lee, K. M. Wu, C. M. Liu, and S. L. Hsu, “Anomalous hot-carrier-induced increase in saturation-region drain current in n-type lateral diffused metal-oxide-semiconductor transistors,” IEEE Trans. Electron Dev., vol. 55, no. 5, pp. 1137-1142, 2008.
[70] J. Kraft, B. Loffler, M. Knaipp, and E. Wachmann, “Hot carrier degradation of p-LDMOS transistors for RF applications,” in Proc. Int. Reliability Physics Symp., pp. 626-627, 2007.
[71] A. Melik-Martirosian and T. P. Ma, “Improved charge-pumping method for lateral profiling of interface traps and oxide charge in MOSFET devices,” in IEDM Tech. Dig., pp. 93-96, 1999.
[72] E. Takeda, Y. Nakagome, H. Kume, N. Suzuki, and S. Asai, “Comparison of characteristics of n-channel and p-channel MOSFET’s for VLSI’s,” IEEE Trans. Electron Dev., vol. 30, no. 6, pp. 675-680, 1983.
[73] A. M. Goodman, “Photoemission of holes from silicon into silicon dioxide,” Phys. Rev., vol. 152, no. 2, pp. 780-784, 1966.
[74] J. F. Zhang, H. K. Sii, G. Groeseneken, and R. Degraeve, “Hole trapping and trap generation in the gate silicon dioxide,” IEEE Trans. Electron Dev., vol. 48, no. 6, pp. 1127-1135, 2001.
[75] S. M. Sze, “Physics of semiconductor devices,” Wiley, New York, 1982.