本論文旨在利用共濺鍍沉積技術製備薄膜電晶體，同時改善介電層與通道層薄膜品質，達到提升元件特性之目的。
本研究主要分為兩部分，第一部分為利用二氧化鋯與氧化鋁作為閘極介電層，使用不同堆疊結構與共濺鍍製程，藉由調變介電層內元素比例調整材料組成與特性，探討不同介面所造成元件之影響，並進一步分析其應用於氧化銦鎵鋅薄膜電晶體之電特性。第二部分則是利用二氧化鈦與氧化銦鎵鋅製備鈦摻雜氧化銦鎵鋅通道層，搭配第一部分所製造出最佳參數之閘極介電層，藉由調變不同功率沉積薄膜，改善元件之可靠度。為進一步提升元件電特性，本研究亦進行介電層與通道層經沉積後熱退火處理(PDA)，探討PDA對材料特性及可靠度之影響。
於第一部分研究中，首先探討堆疊結構介電層應用於氧化銦鎵鋅薄膜電晶體時，不同介面對元件電特性之影響。由實驗結果得知，氧化鋁與氧化銦鎵鋅除具有較佳的介面品質外，亦可藉由熱退火處理改善其遲滯效應。於結合二氧化鋯與氧化鋁之閘極介電層於氧化銦鎵鋅薄膜電晶體之研製上，實驗結果顯示，適當摻入鋁元素於二氧化鋯、且經500 oC退火後氧化鋁鋯介電層仍呈現非晶型態，於相同等效氧化層厚度下具較低漏電流，適合作為電晶體之閘極介電層。
於結合氧化鋁鋯介電層與氧化銦鎵鋅薄膜電晶體部分，實驗結果顯示，摻入適量鋁元素之氧化鋁鋯有助於介電層與氧化銦鎵鋅間界面品質的改善，而過量之鋁元素反而造成界面缺陷增加，對元件特性與遲滯效應產生負面影響。其中以鋁所佔比例為15 %之氧化鋁鋯應用於IGZO-TFT時，可獲得最佳之電晶體特性，元件電流開關比為1.34×107、次臨界擺幅為111 mV/dec、載子遷移率為16.5 cm2/V∙s、介面缺陷密度為1.92×1012 cm-2eV-1與遲滯效應之臨界電壓偏移為0.28 V。此一實驗結果已初步符合本論文於降低關閉電流、提升開關比、改善次臨限擺幅與降低界面缺陷之標的。
於論文第二部分，為改善通道層之缺陷密度，將鈦摻入氧化銦鎵鋅薄膜，以抑制氧空缺的產生。基於鈦原子為易氧化之材料，可捕捉通道層薄膜內之氧分子以降低氧空缺，進而提升元件特性，且具鈦摻雜之氧化銦鎵鋅薄膜，經由高溫退火製程後，不易造成氧原子脫離而形成缺陷，較氧化銦鎵鋅適合高溫退火處理，進一步改善元件電特性及可靠度。
於鈦摻雜氧化銦鎵鋅薄膜電晶體研製實驗結果顯示，摻入適量鈦元素於氧化銦鎵鋅通道可改善薄膜品質，減少薄膜內缺陷密度，其中以Ti(3.5 %)-IGZO TFT且經過400 oC氮氣退火製程下，可獲得最佳電特性及可靠度：元件電流開關比為5.87×107、次臨界擺幅為95 mV/dec、載子遷移率為21.3 cm2/V∙s、介面缺陷密度為1.32×1012 cm-2eV-1以及正負偏壓應力之臨界電壓偏移分別為215 mV和-125 mV。
本論文成功利用共濺鍍法，使用二氧化鋯與氧化鋁的共濺鍍閘極絕緣層製備之薄膜電晶體，並加入鈦摻雜氧化銦鎵鋅之通道層，有效改善漏電流及元件可靠度，提升整體元件特性，有助於未來顯示技術之電子產品特性提升與應用。

SUMMARY
A co-sputtering deposited zirconium aluminum oxide (ZrAlO) gate dielectrics with a dielectric constant ranging from about 26.7 to 15.5 is used for Ti-IGZO thin-film transistors (TFTs). Improved gate controllability and reliability of 50-nm-thick ZrAlO gate dielectrics prepared by a power ratio of ZrO2:Al2O3=100 W:40 W are demonstrated. Using the proposed ZrAlO gate dielectric, it reveals that TFTs with 25-nm-thick Ti-IGZO channel layer exhibit enhanced device performances with subthreshold swing of 95 mV/dec, field effect mobility of 21.3 cm2/V∙s, on/off current ratio of 5.87×107 and positive/negative gate-bias stress of 215 mV/-125 mV, respectively. These performance improvements are attributed to Al incorporation enlarges the energy bandgap of the dielectric and keeps the dielectric layer in amorphous state, and to a considerable reduction in channel defect density after Ti incorporation in IGZO channel.

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