本論文採用半導體製程與元件模擬軟體(Technology Computer Aided Design, TCAD)來研究現今鰭式電晶體(FinFET)所遭遇到的挑戰。和傳統的平面電晶體相比，鰭式電晶體所遭遇到的第一個挑戰是其橫向擴散金氧半電容元件(laterally-diffused MOSFET, LDMOS)的特性較差，這是因為其元件漂移區(drift region)的鰭式結構寬度很小(截面積不足)而導致了高導通電阻的產生，本論文的第三章提出了一種新的製程方法，將原本橫向擴散金氧半電容元件的鰭狀飄移區(fin-type drift region)改成完整的塊狀平面飄移區(bulk planar drift region)，使得導通電阻可以大幅下降，而不減損崩潰電壓。

鰭式電晶體所遭遇到的第二個挑戰是其等效通道寬度只能是非連續的特定值。由於整片晶圓上的所有鰭式電晶體的通道寬度(fin width)與高度(fin height)皆相同，改變鰭的根數是調變電晶體等效通道寬度的唯一方法。由於鰭的根數一定是整數，所以在固定電壓下，電晶體的電流也只能是不連續的特定值。對於靜態隨機存取記憶體來說，其上拉(pull-up)電晶體相較於閘門(pass-gate)電晶體的電流比例(上拉比例pull-up ratio)必須是某個小於1的特定值，才能有最好的寫入能力與良率。然而，當鰭式電晶體的電流只能是特定值的時候，這個比例將難以被達成。本論文的第四章提出了一個新的方法以達成這個比例。藉由插入一個薄的氧化層在鰭通道內，將鰭通道將分割成上通道和下通道。接著，藉由重摻雜上拉電晶體的上通道使其不導通，上拉電晶體的導通電流將由僅存的下通道高度來決定，氧化層的位置越低，下通道高度就越低，上拉電晶體的導通電流由氧化層的位置來決定。

鰭式電晶體所遭遇到的第三個挑戰，在於其短通道效應的抑制能力不足以應付元件的持續微縮。今天，大部份的學者專家都認為，當未來電晶體的閘極長度小於15奈米的時候，現有的鰭式電晶體將被閘極全包覆式電晶體(Gate-all-around transistor)所取代。然而，閘極全包覆式電晶體的缺點在於，奈米線(nanowire)與奈米線間的垂直間距至少需要大於10奈米，才能提供足夠的空間來填充具有一定厚度的功函數金屬(work function metal)。因此，在一樣的元件高度下，所能堆疊的奈米線數目將十分有限，導通電流不高。僅管，有學者專家提出將奈米線拓寬成奈米片(nanosheet)來增加導通電流，這個方式會增加電晶體面積導致成本增加。本論文的第五章提出了一個新的高介電係數插入氧化層鰭式電晶體(high-permittivity inserted-oxide FinFET, iFinFET)來提升電流。藉由利用一個超薄(約3奈米厚)的高介電係數材料來取代原本奈米線間10奈米間距的功函數金屬，相同元件高度下可以堆疊更多的奈米線。

最後，本論文的第六章提出了一種新型態的混合靜態隨機存取記憶體。藉由使用高電流的插入氧化層鰭式電晶體當作閘門(pass-gate)與下拉(pull-down)電晶體，再使用低電流但低漏電的閘極全包覆式電晶體當做上拉(pull-up)電晶體，靜態隨機存取記憶體的上拉比率得以最佳化，使得良率提升，最小操作電壓下降，功率消耗減少，記憶體面積與存取時間保持不變。本論文的第六章也針對了最近提出的叉子記憶體(Forksheet SRAM)進行了完整的分析。

This simulation-based dissertation addresses challenges for the state-of-the-art fin field-effect transistor (FET) and succeeding gate-all-around (GAA) transistors. Compared with the planar-transistor process, the first challenge of the FinFET process is the degraded performance in laterally diffused metal-oxide-semiconductor (LDMOS) FETs due to the higher on-state resistance in the fin-type drift region. This problem is solved in Chapter 3 by incorporating a bulk drift region of the planar LDMOS process into the FinFET LDMOS process so that its on-state resistance is significantly reduced without reducing the breakdown voltage.

The second challenge comes from discrete values of the drive current for the FinFET. For the FinFET, the fin width and fin height are identical for all transistors inside the chip. Changing the number of fins is the only way to adjust the transistor drive strength at a discrete level. Thus, the performance and yield of FinFET-based six-transistor random access memory (6T SRAM) could not be optimized because its pull-up ratio (Ion of pull-up transistors divided by Ion of pass-gate transistors) could not be any value. This challenge is solved in Chapter 4 by inserting a thin buried oxide into the fin to divide it into two separate nanowires (NWs). The upper fin part (upper NW) for the PU transistor is heavily doped to render it nonconductive. The drive strength of the PU transistor is determined by the height of the lower conductive fin part (lower NW) which is determined by the vertical position of buried oxide. Thus, by optimizing the position of buried oxide and heavily doping the upper NWs of the PU transistor, the pull-up ratio of the SRAM could be any value so that the yield and performance of the SRAM are optimized.

The third challenge is the insufficient short-channel effect control of the FinFET when the physical gate length is less than 15 nm. Today, most researchers believe that the GAA nanowire FET (GAA NWFET) will replace the FinFET in the foreseeable future. However, the main drawback of the GAA NWFET is its low on-state current. For the GAA NWFET, the vertical spacing between NWs must be larger than 10 nm to accommodate the work function (WF) metals so that the number of vertical stacked NWs is relatively low. Although the on-state current of GAA NWFET could be enhanced by increasing the NW width to form the nanosheets, it increases the fabrication cost due to larger layout area. In Chapter 5, a new high-permittivity inserted-oxide FinFET (iFinFET) is proposed to increase the current of the GAA NWFET by using an ultra-thin inserted-oxide to replace the WF metal between NWs so that more NWs can be vertically stacked.

Finally, a hybrid 6T SRAM cell is proposed in Chapter 6 by integrating the iFinFET with the GAA transistor. The hybrid 6T SRAM improves the yield and reduces the minimum operating voltage and power consumption without increasing the layout area and memory access time. The recently proposed forksheet SRAM is also analyzed in Chapter 6.

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