隨著半導體元件特徵尺寸不斷接近物理極限，漏電流現象和熱問題愈加突出；且隨著封裝導線尺寸不斷縮小，傳統線路互連所衍生的信號延遲、雜訊和功耗問題愈加嚴重，因而需要發展三維積體技術來延續摩爾定律。作為三維積體電路的核心技術，矽穿孔(Through Silicon Via, TSV)可實現信號在元件堆疊層間的電學連接，縮短連線長度，減小訊號延遲和功耗，縮小晶片佔用面積，實現高度積體化及結合異質晶片的構裝。
本研究分析矽穿孔在高頻信號傳輸情況下之電磁特性，其模型包含銅凸塊(Bump)與金屬線路重佈層(RDL)之組合。第一部分探討TSV堆疊、信號傳輸方式、基板材料、同軸TSV(C-TSV)等信號傳輸行為；第二部分則藉改變TSV中結構之幾何尺寸，包含TSV尺寸、TSV間距、絕緣層厚度、Bump尺寸、RDL尺寸等，研究矽穿孔高頻電磁特性以及各結構參數的影響。
就堆疊之TSV而言，單端信號反射損失為差分信號的2.25倍，矽基板反射損失為玻璃基板的4.18倍，TSV反射損失為C-TSV的1.83倍。

As semiconductor device feature sizes continue to approach the physical limits of materials, leakage current and thermal problems become more problematic while the package pitch continues to shrink. Traditional copper interconnects suffer from increased signal delay, noise, and power consumption issues. Therefore, it is necessary to develop three-dimensional integration technology to continue the Moore's Law. For three-dimensional integrated circuits, the through silicon via (TSV) enables the electrical connection of signals between stacked devices with a shorter length. Hence, signal delay, power consumption, and occupied chip area are reduced to achieve high density and heterogeneous chip integration.
This study analyzes the electromagnetic characteristics of TSV under the condition of high frequency signals. The TSV model includes copper bumps and metal line redistribution layers (RDLs). The first part deals with signal transmission behaviors of TSV stacking, signal transmission modes, substrate materials, and coaxial TSV (C-TSV). The second part examines the geometry effect of TSV, including size, pitch, insulation layer thickness, bump size, and RDL size.
With stacking layers using TSV, the single-ended signal reflection loss is 2.25 times that of the differential signal. The TSV reflection loss of the Si substrate is 4.18 times that of the glass substrate. The TSV reflection loss is 1.83 times that of the C-TSV.

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