| 研究生: |
李軍鑫 Lee, Chun-Hsin |
|---|---|
| 論文名稱: |
以乾式蝕刻運用於矽鍺異質元件之研製 Applying Dry Etching to Fabricate SiGe hetero-devices |
| 指導教授: |
張守進
Chang, Shoou-Jinn 吳三連 Wu, San-Lein |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
| 論文出版年: | 2003 |
| 畢業學年度: | 91 |
| 語文別: | 英文 |
| 論文頁數: | 70 |
| 中文關鍵詞: | 矽鍺 、電晶體 、乾式蝕刻 |
| 外文關鍵詞: | SiGe, FET, DRY ETCHING |
| 相關次數: | 點閱:102 下載:2 |
| 分享至: |
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本論文與日本東京先端科學技術中心(RCAST)合作,以低溫(550℃)固體源分子束磊晶法(SSMBE)成長矽鍺均質摻雜通道場效電晶體元件結構。
採用的摻雜源為硼元素。在磊晶薄膜分析方面,我們分別以二次離子質譜儀與穿透式電子顯微鏡探討硼摻雜層的濃度和各層接面與縱深分佈,並且利用MEDICI二維模擬軟體,模擬本論文中所提元件結構的能帶圖與電洞載子分佈圖,進而判定元件結構優異,找出最佳化之結構。
在實驗方面,我們採用電感式耦合電漿乾式蝕刻法進行矽鍺均質摻雜場效電晶體元件之製作,由於此蝕刻法可獲得高品質蝕刻輪廓,將可大大改善元件電特性。實驗初步結果證實此法可有效抑制元件漏電流,提高元件崩潰電壓。其最高元件互導值為4.2 mS/mm,最大汲極電流可達4.5mA/mm,因此較濕式蝕刻法具有提高元件的電流驅動力。
In our thesis, we cooperated with Research Center for Advanced Science and Technology (RCAST), the University of Tokyo. SiGe doped-channel field effect transistor structures were grown by solid-source molecular beam epitaxy (SSMBE) at low temperature(550°C). Secondary ion mass spectrum (SIMS) and transmission electron microscope (TEM) were used to characterize the properties of structure epitaxial layer, interface profile and layer thickness. We also use a 2D MEDICI software to simulate the energy band diagram and hole concentration distribution corresponding to the device structure.
Inductively coupled plasma (ICP) technique is used to fabricate SiGe hetero- devices in order to improve the electrical property. Experimental results show that the doped-channel FET have higher breakdown voltage, lower leakage current, higher transconductance, and larger current drivability as compared to device obtained by wet mesa etch.
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