疊紋干涉法是一種全場量測位移及應變量的光學技術。利用疊紋干涉法量測所得之條紋分佈形態與數目，並藉由條紋序號的判定，可以直接測得該試件在X方向或Y方向的位移量及應變量。

球陣列式電子構裝中會造成破壞的主要原因是構裝體層的每一層材料間熱膨脹係數大不相同，當晶片運作時會造成晶片溫度上升，造成構裝體內部發生熱應力集中現象，最後導致晶片破壞，因此建立一套量測方法以瞭解構裝體中熱應變的分佈情形，就成為非常重要的課題。

本研究設計出一套疊紋干涉系統來量測構裝體由於溫度變化而產生的熱應變，並配合相位移法及相位展開技術，以提高其條紋解析度和方便分析，最後本文將電子構裝元件因熱應變造成的影響提出建議，以供IC設計人員作為可靠度分析及找出最佳構裝方式之參考。

The method of moire interferometry is a kind of the optical technique of full-field measurement of displacement and strain. We can measure displacement and strain in x-direction and y-direction directly by use of the number and the distribution of the fringes measured by the method of moire interferometry, and by use of the judgement of fringe order.

One of the main factors leds to failure of ball grid array electronic packages is the difference of the coefficient of thermal expansion between materials. The temperature of the chip will rise when the chip works. It causes thermal stress concentration in the interconnections of the package. Finally it induces the chip broke down. Therefore, it is important to establish the measurement method to understand the thermal strain distribution inside the package.

In this paper , the moire interferometry system is designed to detect the thermal strain which caused by temperature change. It uses phase-stepping method and phase-unwrapping technique for improving the resolution and analysis conveniently. Finally, this paper offers a suggestion for the influence of thermal strain to the electronic package. Through this suggestion, we can provide a reliable analysis and find out the best package method for IC designers.

參考文獻

[1] Lord Rayleigh, “On the ,anufacture and theory of diffraction grating”, Phil. Mag. Series4, pp. 81-93, 1874.

[2] J. Guild, The Interference System of Crossed Diffraction Gratings: Theory of Moirè Fringes, Oxford at the Clarendon Press, 1956.

[3]F. M Gerasimov, V. P. Sergeev, I. A. Teltevskii, V. V. Sergeev, B. V. Marichev, “The use of Moirè interference fringes to control the ruling of diffraction gratings.” Opt. Sepectrosc. 19, pp. 152-156, 1956 .

[4]N.Wadsorth, M. Marchant, B. Billing, “Real-time observation of in-plane displacements of opaque surface” Opt. Laser Technol. 5, pp. 119-123, 1973 .
[5]R. Czarnet, “New methods in Moirè interferometry”, PhD dissertation, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, USA,1984.

[6]J. D. Wood, M. Y. Tsai, D. Post, J. Morton, V. J. Parks and F. P. Gerstle, Jr., “Thermal Strains in a Bimaaterial Joint: An Experimental and Numerical Analysis” Proc. 1989 SEM Spring Conference on Experimental Mechanics, pp. 543-551, Society for Experimental Mechanics, Bethel, Connecticut, 1989.

[7]D. Post and J.D. Wood, “Determination of Thermal Strain by Moirè Interferometry”, Experimental Mechanics, pp. 318-322, Sep. 1989.

[8]A. F. Bastawros, A. S. Voloshin, and P. Rodogoveski, “Experimental Validation of fractioal fringe Moirè Interferometry”, Proc. 1989 Society of Experimental Mechanics Spring Conf., Cambridge, MA, May 28-June 1, pp. 406-410,1989.

[9]A.F. Bastawros, A. S, Voloshin, “Mixed Mode stress Intensity Factors by Fractional Fringe Moirè Interferometry”, Proc. 1990 Society of Experimental Mechanics Spring Conf., Albuquerque, NM, June 3-9, pp.69-75, 1990.

[10] B. Han and D. Post, “Immersion Interference for Microscopic Moiré Interferometry”, Experimental Mechanics, Vol.32, No.1, pp.38-41, 1992.

[11]H. C. Choi, Y. Guo, W. LaFontaine, and C. K. Lim, “Solder Ball Connect (SBC) Assemblies Under Thermal Loading: Ⅱ. Strain Analysis via Image Processing, and Reliability Considerations” IBM J. Res. Develop. 37, No. 5,pp.649-659, 1993.

[12]T. Y. Wu, Y. Guo, and T. Chen, “Thermal-mechanical strain characterization for printed wiring boards”, IBM Journal of Research and Development, Vol. 37, No. 5, pp. 621-634,1993.

[13]Y. Guo, et al., “Solder Ball Connect (SBC) Assemblies Under Thermal Loading: Ⅰ. Deformation Measurement via Moirè Interferometry, and its Interpretation”, IBM Journal of Research and Development, Vol. 37, No. 5, pp. 635-648,1993.

[14]Bongtae Han and Yifan Guo, “Thermal Deformation Analysis of Various Elactronic Packaging Products by Moirè Interferometry”, ASME journal of Electronic Packaging, Vol. 118,pp.55-61, Jun. 1996.

[15] Bongtae Han and Yifan Guo , “Determination of an Effective Coefficient of Thermal Expansion of Electronic Packaging Components: A Whole-Field Approach ” , IEEE Trans. On Components, Packaging, and Manufacturing Tech., Part. A,Vol.19, No.2, pp.240-247., June, 1996.

[16] Bongtae Han, Mona Chopra, Seungbae Park, Li Li, and Kaushal Verma, “Effect of Substrate CTE on Solder Ball Reliability of Flip Chip Ball Grid Array Package Assembly ” , Surface Mount International Conf., San Jose, Sep., 1996.

[17] Jiansen Zhu, Daqing Zou, Fulong Dai, Sheng Liu, and Yifan Guo, ”High Temperature Deformation of High Density Interconnectsand Packages by Moiré Interferometry/FEM Hybrid Method”, 1996 IEEE/CPMT Int’l Electronics Manufacturing Technology Symposium, pp.75-83.

[18] Jiansen Zhu, Daqing Zou, and Sheng Liu, ”High Temperature Deformation of Area Array Packages by Moiré Interferometry / FEM HyBrid Method”, IEEE 1997 Electronic Components and Technology Conference, pp.444-452.

[19] Yu-Po Wang, Mani Prakash, and Yifan Guo, ”Three Dimensional Optical Interferometry/Finite Element Hybrid Analysis of a PBGA Package”, EEP-Vol.19-2, Advances in Electronic Packaging－1997 Vol.2 ASME, pp.1767-1774,1997.

[20] Daqing Zou, Jianjun Wang, and Sheng Liu, “CTE Measurement and Delamination Growth by a Time Moiré Technique”, IEEE Electronic Components and Technology Co nference,pp.1124-1127, 1997.

[21] J.Zhu, D.Zou, S.Liu, “Real-Time Monitoring and Simulation of Thermal Deformation in Plastic Package”, ASME Journal of Electronic Packaging, Vol.120, pp. 160-165, Jun. 1998.

[22]J. D. R. Valera, P. G. Sinha, T. Yoshino, O. J. Lokberg, “Large amplitude point-vibration measurement with optical-fiber moiré-based tecnnique”, Optic and Laser in Engineering 31,pp.183-189,1999.

[23] Mikel R. Miller, Xiang Dai, Guotao Wang and Paul S. Ho, “Study of Thermal Deformation in High-Density Eletric Packages Using High Resolution Moiré Interferometry”, Technical Symposium ChipMOS ,pp. 231-236, 2001.

[24] D. Post, B. Han, P. Ifju, High Sensitivity Moire′: Experimental Analysis for Mechanics and Materials. New York: Springer-Verlag, 1994.

[25] Yinyan Wang and Patrick Hassell, 〝Measurement of Thermally Induced Warpage of BGA Packages/Substrates Using Phase-Stepping Shadow Moire,〞 IEEE/CPMT Electronic Packaging Technology Conference, pp.283-289, 1997.

[26] 葉奕銘, 〝相位移數位剪像之相位展開法研究,〞 國立成功大學機械工程學系碩士論文, 2001.

[27] W. W. Macy, 〝Two-Dimensional Fringe-Pattern Analysis,〞 Appl. Opt., 22, pp.3898-3901, 1983.

[28] 謝昌中, 〝疊紋量測技術之建立及應用,〞 國立成功大學機械工程學系碩士論文, 2001.

[29]鄭仲豪, 〝應用相位移陰影疊紋量測高溫下晶圓的變形〞 國立成功大學機械工程學系碩士論文, 2002.

[30] Mikel R. Miller, Ilyas Mohammed,Xiang Dai, Ning Jiang and Paul S. Ho, “Analysis of Flip-Chip Packages Using High Resolution Moiré Interferometry” , IEEE 1999 Electronic Components and Technology Co nference,pp.979-986.