隨著人工智慧、物聯網、自動駕駛與5G等科技持續發展，如何將龐大資料量迅速於系統間相互溝通儼然成為一大課題。為使訊號傳遞路徑縮短，進而提升傳輸速率並減少傳輸過程的損耗，覆晶 (flip chip) 與陣列式 (ball grid array) 的結構成為較佳的構裝方式，其可透過凸塊與錫球作為晶片、基板與電路板之間的溝通媒介，相較於傳統的銲線 (wire bond) 與導線架 (lead frame) 構裝方式，不僅訊號傳遞效率高，更可提供輕、薄、短、小的構裝體。而近年來，無芯基板技術也被開發應用於高頻傳輸產品，其透過移除基板結構中的玻璃纖維層，以降低高頻傳輸時的阻抗 (impedance)，並改善訊號傳遞時的介入損失 (insertion loss)。然而，移除纖維層後的基板，猶如失去鋼筋的水泥結構體，會使基板結構鋼性降低，且對溫度變化相當敏感，易因構裝產生之熱應力導致凸塊崩裂等失效模式。本文主要研究封裝製程中之迴焊冷卻速率、底膠材料性質、烘烤條件及凸塊成分等因子對無芯基板結構及凸塊崩裂的影響。

This thesis focuses on investigation of stress-induced bump crack for flip chip packaging with coreless substrate. Reflow cooling rate, baking and curing condition, underfill material property and bump material composition be consider as the key factors in the study. The microstructure of bump joint was observed with a scanning electron microscope (SEM). Firstly, the higher reflow cooling rate and the fewer high-temperature processes can significantly improve the microstructure of Sn/37Pb bump to resist bump crack. Secondly, the lower CTE and higher elasticity modulus of underfill material can provide good protection and be helpful for avoiding crack initiation even in the reliability test. Finally, the lead free bump is found to provide homogeneous microstructure and good bump joint shape. The experimental results show that the high temperature treatment and the underfill material to the bump protection ability are the most critical conditions for the coreless substrate packaging.

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