本論文提出V-band CMOS毫米波(millimeter-wave)接收機前端子電路的設計，包括：應用於V-band毫米波之低雜訊放大器(low-noise amplifier)、V-band低雜訊放大器及混頻器整合電路和60-GHz寬頻切換式電感壓控振盪器(voltage controlled oscillator)。以上除了60-GHz寬頻切換式電感壓控振盪器僅完成模擬階段，其餘電路設計皆有模擬與量測數據。
論文分為四個部分。第一部分為介紹毫米波系統相關背景和應用，以及提出60-GHz Millimeter-Wave 與MB-OFDM UWB 共存系統的規劃；第二部分為應用於V-band毫米波之低雜訊放大器的電路設計和量測結果，使用製程為TSMC 0.13-µm 1P8M RF CMOS製程。此部份主要內容為用來提升放大器增益的閘極電感增益提升(gate-inductor gain peaking)技術。閘極電感增益提升技術對於低功率消耗的條件下提升毫米波低雜訊放大器的增益是一有效的方法。量測結果顯示，在53 GHz時，小訊號增益為21 dB，雜訊指數為7.6 dB，3-dB 頻寬為51.3 ~ 55.8 GHz，輸入1-dB增益壓縮點為 -25 dBm，輸入之三階交錯點(input third-order interception point, IIP3)為 -16 dBm，供應電壓VDD為1.5 V，整體消耗功率為15.1 mW，且FOM為0.95。
第三部分為整合低雜訊放大器和V-band雙平衡式吉伯特混頻器(double balanced Gilbert-cell mixer)，以實現60-GHz MMW與UWB共存系統之接收機前端電路，使用製程為TSMC 0.13-µm 1P8M RF CMOS製程。在此，低雜訊放大器的結構係採用相同於第二部份的放大器結構，混頻器的架構則是雙平衡式吉伯特型式。低雜訊放大器和混頻器的部分，皆有個別的量測數據。最後整合的接收機電路則僅有部分量測數據，目前還在量測的階段。
第四部分為提出一個具有創新切換式電感的60-GHz寬頻壓控振盪器，使用TSMC 90-nm 1P9M RF CMOS製程環境來設計。對於被動元件共振腔的設計，我們提出創新的切換式電感架構，可部分代替可變電容(varactor)元件調變頻率的功能。利用此切換式電感就能獲得寬頻的調變振盪頻率範圍，且兼具低相位雜訊(phase noise)之特性表現。量測結果顯示，供應電壓VDD為1.2 V，核心電路的消耗功率為16 mW，主要振盪頻率為 60 GHz，相位雜訊在10 MHz偏移頻率下為-116 dBc/Hz，調變振盪頻率範圍約為10 GHz (約為17%)，FOM (figure of merit)為-180 dBc/Hz，FOMT (figure of merit with tuning range)為-185 dBc/Hz。

This thesis presents the V-band CMOS millimeter-wave (MMW) receiver RF front-end function block designs, including a V-band CMOS low noise amplifier (LNA) for millimeter-wave application, an integration of V-band LNA and mixer, and a design of 60-GHz wideband switched-inductor voltage controlled oscillator (VCO). Except of the VCO, the LNA and receiver front-end circuit both have been simulated and measured.
This thesis can be divided into four parts. In the first part, we introduce the backgrounds and applications for MMW system and the structure plan of 60-GHz MMW and MB-OFDM UWB co-existence system. The second part of this thesis presents the design and measurement results of an MMW LNA. The LNA was fabricated in TSMC 0.13-µm 1P8M RF CMOS process. The main content is gate-inductor gain peaking technique for increasing LNA gain. The gate-inductor gain peaking for LNA design, which is an effective way to achieve the high gain performance with low power consumption. The measurement data show that the LNA can achieve a peak gain of 21 dB and a noise figure (NF) of 7.6 dB at 53 GHz, a 3-dB frequency bandwidth ranging from 51.3 to 55.8 GHz, an input 1-dB compression point (P1dB) of -25 dBm at 53 GHz, and an input third-order intercept point (IIP3) of -16 dBm. Also, the LNA consumes only 15.1 mW at a supply voltage of 1.5 V. The calculated figure-of-merit (FOM) is 0.95.
The third part of the thesis, we present an integration of LNA and mixer for 60-GHz MMW and MB-OFDM UWB co-existence system receiver. The topology of the LNA is similar to that proposed in the second part. The topology of the mixer is Gilbert-cell type. The measurement data for LAN and mixer are shown individually. The measurement of the whole integration circuit is still under going.
In the fourth part, we present the design of a 60-GHz wideband switch-inductor voltage control oscillator, which was fabricated in TSMC 90-nm 1P9M RF CMOS process. For the passive elements, the switched inductor for VCO design which is an effective way to achieve the wideband tuning range performance with low phase noise. The VCO consumes only 16 mW at a supply voltage of 1.2 V, whose designed oscillation frequency is of 60 GHz and which achieves a phase noise of -116 dB at 10 MHz offset, and a tuning range of 17 %. The calculated FOM is -180 dBc/Hz and FOMT is -185 dBc/Hz, respectively.

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