本論文旨在進行具堆疊通道結構(Double channel structure, DCS)及於背通道表面沉積p-型氧化鎳(NiO)覆蓋層(Capping layer, CL)下閘極結構氧化矽鋅錫(Si-Zn-SnO, SZTO)薄膜電晶體(Thin film transistors, TFTs)與場效應二極體(Field effect diodes, FEDs)之元件製備，並作為紫外光感測器(Ultraviolet photodetectors, UV-PDs)之應用。為改善元件特性，藉由高/低載子濃度的適化堆疊通道結構設計以提升通道膜厚(增加光生載子生成空間)並增加通道空乏能力，另亦結合NiO CL於背通道形成pn異質接面以進一步降低通道有效厚度(抑制暗電流I_dark)並於照光過程產生額外大量光生載子(提升光電流I_ph)，提升元件靜態與光響應特性及可靠度。
研究過程中，首先，藉由通道薄膜濺鍍製程氬/氧氣流量比例(Oxygen flow ratio, OFR=(O_2/(A_r+O_2))×100 %)之調變製備出OFR(0%)、OFR(20%)、OFR(30%)與OFR(40%)-SZTO TFTs，除針對不同OFR-SZTO薄膜材料特性分析比較外，並進行所製備TFTs元件電性與可靠度之分析與探討。其次，依據上述不同OFR-SZTO TFTs所展現場效移動率(field-effect mobility, μ_FE)與可靠度之折衷關係，結合具最高μ_FE之高載子濃度OFR(0%)-SZTO薄膜及具最佳可靠度之低載子濃度OFR(30%)-SZTO薄膜分別作為通道底層與上層之最適化堆疊通道結構；先使用OFR(0%)-SZTO製備出具不同通道底層膜厚(T_BL=30、40及50 nm) SZTO TFTs與FEDs (分別定義為Type A-30、A-40與A-50 TFTs與FEDs)，以探討T_BL於元件光電特性之影響。於使用通道增厚而處於部分空乏狀態之Type A-40與Type A-50 TFTs結合具低載子濃度OFR(30%)-SZTO上層膜厚(T_UL=10、30、40及50 nm)以製備DCS-SZTO TFTs與FEDs，將探討堆疊結構T_BL與T_UL於元件靜電特性及感光感測特性之影響。
有鑑於本研究於最適化堆疊通道結構上，T_UL堆疊於增厚之T_BL所產生空乏能力受限，為能於提升膜厚以增加光生載子數量並可達抑制暗電流(I_dark)，本研究以T_BL= 50 nm 與T_UL= 0~50 nm (Type B-50-(0~50) TFTs)之堆疊通道結構結合NiO CL，探討所製備NiO CL/DCS-SZTO TFTs與FEDs (Type C-50-(0~50)-CL TFTs與FEDs)之有無NiO CL於元件電性及光感測性能之影響，此外亦進行TFTs與其對應FEDs之光電特性比較。最後，本研究以Type A-30、Type A-50、Type B-50-30與Type C-50-30-CL TFTs與FEDs於負偏壓應力(Negative bias stress, NBS)進行元件之可靠度分析，探討其〖∆V〗_th及〖∆I〗_D 大小並進行TFTs與FEDs之優劣比較。
本論文架構將主要研究內容分為「不同OFR通道薄膜製備之SZTO TFTs材料特性、元件電性及可靠度分析」、「堆疊通道結構之SZTO TFTs 與FEDs電性及光感測性能分析」、「具圖案化NiO CL於堆疊通道結構SZTO TFTs與FEDs電性及光感測性能分析」與「堆疊通道結構SZTO TFTs與FEDs於沉積NiO CL前後之可靠度分析」等四大項，研究成果與討論茲依序分述如下：
於「不同OFR通道薄膜製備之SZTO TFTs材料特性、元件電性及可靠度分析」之研究上，實驗結果顯示，於SZTO通道薄膜材料特性上，載子濃度與氧相關缺陷(V_O)均隨著OFR的提升而呈現下降趨勢，OFR(0%)-SZTO薄膜具有最高載子濃度(2.8×〖10〗^18 cm^(-3))、移動率(48.2 cm2/V‧s)與V_O (27.3%)；相對地，OFR(30%)-SZTO薄膜則呈現較低載子濃度(3.2×〖10〗^17 cm^(-3))、較低移動率(22.8 cm2/V‧s)與V_O (18.9 %)之相反趨勢；於元件電特性及可靠度上，在所製備元件中，OFR(0%)-SZTO TFT具有最高載子濃度及較優元件電性，其I_off、I_on⁄I_off 、V_th、SS、μ_FE及R_ch分別為4.08×〖10〗^(-12) A、3.48×〖10〗^7、0.34 V、120 mV/dec、28.7 cm2/V･s及4.37 kΩ；然而OFR(30%)-SZTO TFT卻具有較低載子濃度及較佳可靠度之優勢，其遲滯電壓偏移(∆V_Hys= 54 mV)及於正/負偏壓應力(PBS/NBS)進行1000 s測試下之臨界電壓偏移(∆V_th=128/-119 mV)，均歸因於較佳的通道薄膜品質而呈現出最佳之可靠度；為有利於元件光電特性之展現，於後續堆疊通道結構設計上之底/上層分別採用OFR (0%)/OFR (30%)-SZTO 作為通道薄膜材料。
於「堆疊通道結構之SZTO TFTs與FEDs電性及光感測性能分析」之研究上，旨在探討堆疊通道結構於元件電性及光感測性能之影響。首先，針對單層通道厚度(T_ch)於傳統型SZTO TFTs元件電特性之影響上，實驗結果顯示，Type A-30 TFT (T_ch= 30 nm)於熱平衡時處於全空乏狀態且呈現較優越靜電特性，其I_off、I_on⁄I_off 、V_th、SS、μ_FE及R_ch分別為4.08×〖10〗^(-12) A、2.87×〖10〗^7、0.34 V、130 mV/dec、28 cm2/V･s及4.37 kΩ)；且於275 nm波長照光下具有光靈敏度S_ph (7.53×〖10〗^4 A/A)、光響應度R_ph (6.14 A/W)及光偵測率D^* (3.34×〖10〗^13 Jones)之光感測性能。相較於Type A-30 TFT，Type A-40與Type A-50 TFTs (T_ch分別40與50 nm)因T_ch的增加造成V_th左移而處於部分空乏狀態，雖於I_on (3.53×〖10〗^(-4)與6.73×〖10〗^(-4) A)及μ_FE (35.8與43.1 cm2/V･s)有所提升，但相對地亦使I_off (3.88×〖10〗^(-11)與3.06×〖10〗^(-10) A)呈指數性大幅提升，故呈現出較低 I_on⁄I_off (9.1×〖10〗^6與2.2×〖10〗^6)；於UV光感測性能上，Type A-50 TFT因具有較大的光生載子生成空間使整體I_D較高，導致其I_ph及I_dark亦提高，故具有較大的R_ph (27.4 A/W)以及較小的S_ph (4.48×〖10〗^3A/A)與D^* (6.91×〖10〗^12 Jones)。
根據上述實驗結果，將處於部分空乏之Type A-40與Type A-50 TFTs採用堆疊通道結構設計，於上層分別沉積10、30、40及50 nm薄膜厚度(T_UL)，並探討元件電性及光感測性能。實驗結果顯示，所製備元件中，Type B-40-30與Type B-50-30 TFTs分別於該型元件中呈現出較佳電特性，其I_off、I_on⁄I_off 、V_th、SS、μ_FE及R_ch分別為5.5×〖10〗^(-12)與6.1×〖10〗^(-11) A、1.96×〖10〗^7與4×〖10〗^6、0.47與0.09 V、103與112 mV/dec、27.6與32.7 cm2/V･s及3.51與2.17 kΩ，可歸因於適化堆疊結構所形成一nn^-高低接面，底層通道因具較高電子濃度藉擴散作用傳送至較低電子濃度之上層通道，以增加主動層通道之空乏能力；然而於較厚T_UL(40與50 nm)所製備DCS-SZTO TFTs元件將因電流傳導路徑的增加而導致元件之截止電流的提升，使元件電性劣化；於275 nm波長照光下Type B-40-30與Type B-50-30 TFTs具有S_ph (3.38×〖10〗^5與5.69×〖10〗^4 A/A)、R_ph (37.27與69.5 A/W)及D^* (2.14×〖10〗^14與9.94×〖10〗^13 Jones) 較佳之光感測性能，相較於Type A-30 TFT元件之R_ph及D^*皆大幅提升，主要歸因於整體膜厚之提升於照光下增加光生EHP之數量，以提升元件之I_ph。
於「具圖案化NiO CL於堆疊通道結構SZTO TFTs與FEDs元件電性及光感測性能分析」之研究上，有鑑於Type B-50-(0~50) TFTs於熱平衡下通道皆處於部分空乏，故本研究項目旨在利用p-NiO材料沉積於堆疊結構上以製備Type C-50-(0~50)-CL TFTs，並進行元件之光電特性分析與比較。實驗結果顯示，Type C-50-(0~50)-CL TFT與FED於熱平衡時處於全空乏狀態且呈現較優越靜電特性，其中TFT之I_on⁄I_off 及 μ_FE分別為1.33×〖10〗^7及27.6 cm2/V･s，而FED則呈現出I_F⁄I_R 為1.2×〖10〗^7之整流行為。於275 nm波長照光下，Type C-50-30-CL TFT與FED之S_ph、R_ph及D^*分別為1.07×〖10〗^7 (9.43×〖10〗^6) A/A、1672 (1623) A/W與6.8×〖10〗^15 (6.12×〖10〗^15) Jones。相較於Type A-30 TFT與FED，Type C-50-30-CL TFT與FED於提升T_BL前提下可藉由堆疊通道結構及NiO CL之適當設計以降低通道有效厚度，使通道增厚仍可處於全空乏狀態而具有相近之低I_off，且因I_ph大幅提升而具有極為優越之光感測性能。
於「堆疊通道結構SZTO TFTs與FEDs於沉積NiO CL前後可靠度分析」之研究上，本研究項目旨在藉由上述所製備之Type A-30、Type A-50、Type B-50-30及Type C-50-30-CL TFTs與FEDs等四種元件進行負偏壓應力(Negative bias stress, NBS)測試之可靠度分析，並進行TFTs與FEDs之可靠度優劣比較。實驗結果顯示，相較於Type A-30 TFT，Type A-50 TFT元件於NBS進行1000 s應力測試後呈現出∆V_th(由-216 mV降至-144 mV)與∆I_D(由121降至11.8)之較佳可靠度，主要歸因於通道膜厚的增加使通道薄膜品質獲得改善，並同時降低介電/通道層界面之缺陷密度。相較於Type A-50 TFT，Type B-50-30 TFT元件於NBS進行1000 s應力測試後呈現出∆V_th (由-144 mV降至-91 mV)與∆I_D (由11.8降至2.45)之較佳可靠度，可歸因於堆疊結構之上層有效降低底層通道上表面之缺陷密度，以改善堆疊通道之介面品質，減少界面陷補電荷數量，進而有效降低∆V_th及∆I_D。
值得注意的是，Type A-50 TFT與Type C-50-30-CL TFT之∆V_th、∆I_D於不同應力時間下幾乎相同，其中1000 s時分別呈-91及-93 mV、2.45及2.48，可歸因於NBS造成之∆V_th、∆I_D主要來自介電/通道層界面之陷補電荷，而處於堆疊通道上之CL幾乎不受閘極偏壓作用，因此對∆V_th 、∆I_D大小不會產生影響。
對FEDs而言，相較於Type A-30 FED，Type A-50 FED與Type B-50-30 FED元件於NBS進行1000 s應力測試後呈現出∆I_D(分別由71.7降至4.65與1.15)之較佳可靠度，主要歸因於Type A-50 TFT與Type B-50-30 TFT之可靠度優於Type A-30 TFT，並影響其相對應FED特性。而沉積CL後，因其不受閘極偏壓影響，故Type B-50-30 FED與Type C-50-30-CL FED元件之∆I_D變化不大，於應力時間1000 s下分別為1.15及1.13。故總結，FEDs之〖∆I〗_D皆小於相同結構參數之TFTs，主要歸因於兩元件同屬MOS結構又因FEDs特殊的偏壓條件(V_G=V_D (或V_S))使得垂直的平均電場強度較低，故相較於TFTs，FEDs之∆I_D相對較少，Type C-50-30-CL FED之∆I_D相較於對應的TFT減少約53%，故可判斷FEDs於NBS下之電性穩定度較優。
本論文以具優異電特性之Hf0.82Si0.18O/SZTO TFT作為平台，成功製備出下閘極NiO CL/DCS-SZTO TFTs與FEDs，並作為UV PDs之應用，透過DCS及NiO CL適化結構設計使元件具有優異之光電特性。於所有製備元件中，Type B-50-30-CL FED於275 nm波長照光下呈現出S_ph (9.43×〖10〗^6 (A/A))、R_ph (1623 (A/W))及D^* (6.12×〖10〗^15 (Jones))之最佳光感測性能。於TFTs與FEDs UV-PDs之操作便利性與光電特性上，相較於TFTs，FEDs具有製備方式簡易，成本低廉之優勢外，且FEDs之單一偏壓操作方式可獲得穩定之I_R，於應用上得以操作在較低V_D實現低功耗，並減少電路設計之複雜度；然FEDs的光電特性取決於其相對應之TFTs，若TFTs元件之V_on可操作於(V_G=0 V)，此時其對應之FEDs所呈現之I_R將會小於TFT的I_off，FEDs UV-PDs也將具有優於TFTs UV-PDs之光感測性能，故本論文所提NiO CL於堆疊通道結構SZTO FEDs之光感測應用領域具有創新性與發展潛力。

The electrical properties of Sn-Zn-SnO (SZTO) thin-film transistors (TFTs) and field effect diodes (FEDs) based on a double channel structure (DCS) with different carrier concentrations and a patterned NiO capping layer (CL) deposited on the surface of the back channel are investigated, and their application in ultraviolet photodetectors (UV-PDs) to clarify the photo detection performance are also studied . Experimental results indicate that the proposed SZTO TFT (FED) UV-PDs based on DCS with a high carrier concentration and 30-nm-thick upper layer (T_UL) stacked on a high carrier concentration and 50-nm-thick bottom layer (T_BL) as well as a patterned p-NiO CL, denoted as a type C-50-30-CL TFT (FED), has excellent detection performance in photoresponsivity and photosensitivity up to 1672 (1623) A/W and 1.03×〖10〗^7 (9.43×〖10〗^6) A/A under illuminated at 275 nm, which increased by about 272 (262) and 137 (123) times than the conventional SZTO TFT (FED) with T_ch of 30 nm. These improvements are due to the use of DCS increase the space for UV illumination and the use of NiO CL lowers the dark current and causes a considerable negative threshold voltage shift under UV irradiation to significantly boost the photocurrent. Note that, Among the fabricated devices, the type C-50-30-CL FED exhibits the best stability with a lower variation of the drain current (∆I_D) of 2.48 A/A under negative bias stress (NBS) at -4 V for 1000s, which due to thicker SZTO channels reduce trap density, thereby reduces the ∆I_D. The proposed NiO CL/DCS-SZTO FED is expected to have significant potential in advanced UV-PDs applications.

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