隨著 5G/6G 技術與雷達通訊聯合系統(Joint Radar-Communication, JRC)的快速發展，雷達感測系統對頻率合成器的相位雜訊、鎖定時間與功耗等關鍵效能指標上的要求日益嚴苛。次取樣鎖相迴路（Sub-sampling Phase-Locked Loop, SS-PLL）因具備優異的頻寬內相位雜訊特性，逐漸成為雷達感測應用的研究重點。然而，次取樣架構本身受限於取樣相位偵測機制，其有效相位偵測範圍有限，在初始頻率誤差較大時容易發生相位模糊或錯誤判定，導致鎖定時間顯著增加，成為其實際應用上的主要限制之一。
本論文針對雷達感測應用需求，設計並實作兩顆操作於 4.8 GHz 頻段之次取樣鎖相迴路。該頻段具備良好的雜訊特性，且可透過五倍頻技巧升頻至 24 GHz，用於雷達感測系統，因此選定為本研究之設計目標頻段。兩顆晶片皆採用 TSMC 0.18 μm CMOS 製程實作，參考頻率為 75 MHz。
第一顆晶片採用單一充電泵之次取樣鎖相迴路架構，並藉由數位控制機制有效降低系統功耗。量測結果顯示，在 1.8 V 供應電壓下，其核心功耗僅為 7.4 mW，相位雜訊在 1 MHz 頻率偏移處為 −102.16 dBc/Hz。然而，實際量測顯示由自由振盪狀態鎖定至目標頻率約需 6 µs，此結果顯示本晶片設計在缺乏額外快速收斂機制的情況下，鎖定時間的快慢受到次取樣相位偵測器在大相位誤差條件下較難正確捕獲相位誤差的影響。
為克服鎖定速度的限制，第二顆晶片利用正交次取樣相位偵測器器（Quadrature Sub-sampling Phase Detector, QSSPD）與快速鎖定架構。該設計透過正交壓控振盪器產生四相（I/Q）訊號，利用多相資訊進行區域判定，以擴展有效相位偵測範圍並降低相位模糊問題。此外，系統在啟動階段主動開啟輔助鎖頻迴路，快速將振盪頻率拉近目標值，以顯著縮短頻率收斂時間；當系統進入穩態後，該輔助路徑將自動關閉，使系統回歸次取樣鎖相迴路之低雜訊特性，避免對穩態相位雜訊造成劣化。實測結果顯示，第二款晶片在1.8 V供應電壓下運作，其核心功耗為9.4 mW，但換得顯著的鎖定速度提升。量測結果顯示，其鎖定時間成功縮短至0.86 µs，相較於第一代設計提升約6至7倍，驗證所提出快速鎖定架構之有效性。同時，在相位雜訊表現方面並未出現明顯劣化，顯示該方法能在維持低雜訊特性的前提下，有效改善次取樣鎖相迴路的鎖定瓶頸。

With the rapid development of 5G/6G technologies and joint radar-communication (JRC) systems, rader sensing systems demand stringent performance from frequency synthesizers in terms of phase noise, locking time, and power consumption. Sub-sampling phase-locked loops (SS-PLLs) have emerged as a promising solution due to their superior in-band phase noise. However, their limited phase detection range under large initial frequency errors leads to long locking times, which remains a critical challenge.
This thesis presents the design and implementation of two sub-sampling phase-locked loops operating at 4.8 GHz for radar sensing applications. The 4.8 GHz band offers favorable noise performance and can be upconverted to 24 GHz through frequency multiplication by a factor of five, making it suitable for radar systems. Therefore, it is selected as the target operating frequency of this study. Both chips are fabricated in TSMC 0.18 μm CMOS technology, with a reference frequency of 75 MHz.
The first design adopts a single charge-pump SS-PLL architecture with digital control to reduce power consumption. Measurement results show that it achieves a phase noise of −102.16 dBc/Hz at 1-MHz offset while consuming 7.4 mW from a 1.8-V supply. However, due to the absence of a fast acquisition mechanism, the locking time from free-running to the target frequency is approximately 6 μs.
To address this limitation, the second design incorporates a quadrature sub-sampling phase detector and a fast-locking scheme. By utilizing quadrature VCO outputs for region detection and enabling an auxiliary frequency-locking loop during acquisition, the proposed approach significantly accelerates frequency convergence. The auxiliary loop is automatically disabled after lock to retain the inherent advantages of the SS-PLL. Operating at 1.8 V, the prototype consumes 9.4 mW and achieves a reduced locking time of 0.86 μs, representing a 6–7× improvement over the first design without noticeable degradation in phase noise performance.

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