心臟是人體中最重要的器官之一，因此知道其生理訊號變化，對醫師在做診斷時是非常重要的，而利用心電圖(Electrocardiogram, ECG)來觀察心臟的狀況是目前公認最簡便且最廣為使用的方法。由於心電圖各波形之形狀及其間隔皆與心臟產生訊號之電氣特性有直接關係，所以可以藉由認出心臟訊號電氣活動中的異常，來診斷出許多不同的心臟疾病，而且可以用來監測病人的安危、評估病情發展和治療成效等。

一個心跳週期的心電圖波形中，又以QRS複合波最為顯著，所以一般來說，在心電訊號分析工作中，又以QRS複合波的偵測最為重要，而關於如何偵測心電圖中QRS複合波的演算法種類繁多，例如：類神經網路、小波轉換、樣板比對濾波器等等。這些方法的應用，都有其特定的條件與限制，且在考慮電路實現的複雜度下，許多演算法將過於複雜而不適合電路實現。

據此，本研究目的在完成此一個以差分運算法為基礎之QRS複合波即時偵測電路架構的設計，其使用相對簡易的演算法，在MATLAB/Simulink軟體環境完成模擬之後，便著手進行硬體電路架構的設計與實現。在硬體設計層級，我們使用Verilog硬體描述語言進行電路設計，完成後以MIT-BIH心律不整資料庫所提供之心電訊號來進行電路的模擬與驗證，結果顯示我們所設計之電路能正確無誤地進行QRS複合波即時偵測的工作。就實現層面而言，本次研究使用TSMC 90奈米的製程技術實現硬體電路，並在暫存器轉移階層(register transfer level, RTL)評估本架構之效能。此外，亦使用現場可程式化邏輯閘陣列(field-programmable gate array, FPGA)實現及驗證本研究之硬體架構。

The QRS detection is an entry point for almost all the electrocardiogram (ECG) applications. Due to complexity of their mathematical computation, many QRS detectors are implemented by using software and cannot operate in the real-time fashion. This paper presents a new simple and efficient hardware architecture design and implementation of real-time QRS complex detection based on difference operation method(DOM). After simulations verified by MATLAB program, we use Verilog HDL to perform the task of hardware design. The hardware design is tested with ECG records obtained from the MIT-BIH arrhythmia database. The achievable accuracy exceeds 99% for records including some typical and worst cases in the database.

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