研究生: |
黃以芹 Huang, I-Chin |
---|---|
論文名稱: |
一種具環繞式閘極與超薄通道之新穎場效電晶體及其模擬分析 Study of A Novel Gate-All-Around Ultra-Thin Body Field Effect Transistor (G-UTBFET) |
指導教授: |
王水進
Wang, Shui-Jinn |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 微電子工程研究所 Institute of Microelectronics |
論文出版年: | 2018 |
畢業學年度: | 106 |
語文別: | 中文 |
論文頁數: | 105 |
中文關鍵詞: | 環繞式閘極 、超薄通道 、場效電晶體 、TCAD模擬 、製程變異 、靜態隨機存取記憶體 |
外文關鍵詞: | Gate all around, Ultra-thin body, TCAD Simulation, Variation, 6T-SRAM |
相關次數: | 點閱:130 下載:15 |
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於提升數位積體電路的速度、功能與降低製作成本要求下,元件尺寸持續微縮遂衍生諸多的短通道效應,造成元件特性劣化。為改善此問題,本論文提出一種具環繞式閘極(Gate-all-around, GAA)與超薄通道(Ultra-thin-body, UTB)之新穎場效電晶體,稱G-UTBFET,透過增加閘極對通道的控制能力與降低關閉狀態之漏電電流,有效改善元件短通道特性,使元件於7 nm製程節點仍可獲得極優異的性能。
本論文所使用之半導體元件模擬軟體為Sentaurus TCAD,而供應電壓與等效氧化層厚度等參數皆參考2015國際半導體技術指標於7 nm節點之預測,為使分析結果更接近實際狀況,模擬時皆有加入量子效應相關之物理模型。
本研究首先針對G-UTBFET於不同摻雜型態、結構參數以及絕緣柱材料下元件特性之分析,結果顯示反轉型或累積型的摻雜型態能夠獲得較佳的靜電特性,而使用較小的通道厚度、絕緣柱直徑以及較低介電係數之中央絕緣柱材料有助於提升G-UTBFET的元件特性。此外,若將源極延伸區與閘極正交疊(Overlap)、汲極延伸區與閘極負交疊(Underlap),除了能夠進一步優化元件之開關特性,也能在不改變閘極電容的狀態下提升元件之驅動電流並改善研本質延遲。我們亦將G-UTBFET與絕緣層上超薄通道場效電晶體及環繞式閘奈米線電晶體進行短通道特性的比較,不論係在7 nm或是更先進之技術節點,本論文所提出之G-UTBFET元件皆最具潛力。
對於奈米級之電晶體元件,基於隨機摻雜擾動與製程所帶來的變異性將嚴重關係到其應用於積體電路上之可能性,本研究亦討論隨機摻雜變異及通道厚度變異對於G-UTBFET元件特性的影響。我們發現反轉型G-UTBFET由於通道為無摻雜,對於隨機摻雜擾動有較好的抑制能力,而無接面式G-UTBFET對於隨機摻雜擾動的變異性較為嚴重,主要是因為其通道內之雜質數目較少,元件特性對於雜質的分布位置變得更加敏感所致。另外,在通道厚度變異方面,反轉型與無接面式G-UTBFET皆具有有不錯的抗擾動能力,主要可歸因於G-UTBFET元件具有極佳的通道控制能力。本研究亦針對G-UTBFET結構之介面及通道缺陷對元件特性的影響進行分析,隨著缺陷位置靠近汲極其變異程度將會減弱,而缺陷位於「通道中央」及「通道-絕緣柱介面」上對於特性的影響又較缺陷位於「介電層-通道介面」來得大,因此如何控制及優化通道及其內側之品質對於G-UTBFET應用於電路上係相當重要的課題之一。
最後,本研究也評估了G-UTBFET應用於反相器及6T靜態隨機存取記憶體之性能。於反相器應用方面,結果顯示結構參數的變化對於其雜訊邊界並較無太大之影響,但於6T-SRAM方面,改變通道厚或絕緣柱直徑可優化其讀寫效能,然而,此舉亦將改變電路之操作速度以及消耗功率,故在選擇參數時,除了在讀寫之間取捨外,也必須考慮其於操作速度及消耗功率上之代價。
不論是於靜電特性或數位電路應用上,本論文所提出之G-UTBFET元件都具備較為優異之特性,對於新世代技術節點或摩爾定律之延伸將可提供助力。本論文已完成有關所提出G-UTBFET基本元件特性與重要參數之探討分析,研究成果可供半導體產業進行最適化製程之開發及更先進積體電路之應用參考。
An advanced vertical FET comprising of a gate all around (GAA) and ultra-thin body (UTB) structure (called G-UTBFET) is proposed in this study. Simulation results based on Sentaurus TCAD considering quantum confinement effects are presented and discussed. Following 7 nm node technology, the proposed G-UTBFET shows the lowest values in Ioff, SS (64.2 mV/dec) and DIBL (13.3 mV/V) as compared with planar ultra-thin-body FET (UTBFET) and nanowire FET (NWFET), with an average reduction of 42%, 7.5%, and 40%, respectively, are achieved. The superiority in G-UTBFET performance is attributed to the realization of UTB nanotube (NT) via insulator pillar placement and strong enhancement in electrostatics with GAA configuration.
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