隨著半導體製程節點不斷向前推進，晶片的運算速度也越來越快，更加凸顯了解決馮紐曼瓶頸的重要性，為了減少CPU與記憶體間資料傳輸所浪費的能耗與時間，近年來「記憶體內運算」被廣泛的討論與研究。其中，基於氧化鉿的鐵電材料應用在電晶體上除了具有非揮發性的特色之外，還有高耐受度、讀寫速度快、低能耗以及與CMOS製程兼容等特色，因此被視為是能實現記憶體內運算的熱門人選。
本論文使用了Sentaurus TCAD 2019版本中的Sprocess來建構獨立雙閘極鐵電電晶體模型，為了增加模擬結果的真實性，利用了從TSRI實際製程製作的鐵電電晶體量測得到實驗數據，從中萃取得到通道外串聯電阻、飽和電流與閾值電壓，再將建構好的模型與之擬合。接著設計出記憶體陣列的電路並畫出佈局圖，此陣列透過三條控制線來操作，利用前閘極、後閘極、汲極和源極間的電場交互作用來決定是否寫入或抹除儲存在元件中的資料，最大的特色是每個記憶單元只需要一顆元件，不需要額外的電晶體來控制讀寫，在面積上相對具有優勢。
在確定陣列能正常操作之後，為了增加陣列大小以提升運算效能，必須使元件有更大的開關比，因此對元件結構與操作方式進行了一系列的優化與探討，包括二氧化矽的厚度、通道的長寬高、操作電壓與時間，從中證實了此元件在微縮後依然有著優異的性能，更能與先進製程相容。應用上除了記憶體內運算之外，也能在傳統計算機系統架構中憑藉其讀寫速度上的優勢，取代一部份的快閃記憶體，提升系統性能。在元件可靠度的部分，針對氧化層介面附近的固定電荷來做討論，了解它會對元件的特性與記憶體陣列有什麼影響。

關鍵字： 記憶體內運算、非揮發性記憶體、獨立雙閘極鐵電電晶體、鐵電記憶體陣列、固定氧化層電荷

With the continuous advancement of semiconductor process nodes, the computing speed of chips is getting faster and faster, which highlights the importance of solving the Von Neumann bottleneck. To reduce the energy consumption and time wasted in data transmission between CPU and memory, “Computing-in-Memory” is widely discussed and researched in recent years. Among them, the applications of hafnium oxide-based ferroelectric materials in transistors have the characteristics of high endurance, fast read and write speed, low energy consumption, and compatibility with CMOS processes, in addition to non-volatile features. Therefore, the ferroelectric material transistor is regarded as a popular candidate for realizing Computing-in-Memory.
This paper uses Sprocess in the Sentaurus TCAD 2019 version to construct an independent double-gate FeFET model. To increase the authenticity of the simulation results, the model is also fitted to the experimental data obtained from the actual process in TSRI. Moreover, it includes saturation current, threshold voltage, and series resistance. The circuit and layout of the memory array are demonstrated in this paper. The array is operated through three control lines. The interaction of the electric field between the front gate, back gate, drain, and the source is used to determine whether to write or erase. The most prominent feature is that each memory cell only needs one device. No additional transistors are required to control the reading and writing, which makes it relatively advantageous in the area.
After confirming that the array can operate normally, to increase the size of the array to improve the computing performance, the device must have a larger ON/OFF ratio. Therefore, we optimize the device structure and operation methods, including the thickness of oxide, the length, width and height of the channel, the operating voltage, and the time. We prove that this device still has excellent performance after shrinking, and it is compatible with advanced processes. In addition to Computing-in-Memory, it can also replace a part of flash memory in computer architecture. In the detail of device reliability, we discuss the fixed charge near the interface of the oxide layer to understand how it affects the characteristics of the device and the memory array.

Keyword: Computing-In-Memory, non-volatile memory, independent double-gate FeFET, ferroelectric memory array, fixed oxide charge

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