本論文主要研製24-GHz鎖相迴路之壓控振盪器，以及24-及60-GHz寬頻除頻器。論文探討不同架構之壓控振盪器與除頻器的特性，並提出不同電路設計方式來改善電路之效能。
24-GHz改良式考畢茲壓控振盪器採用TSMC 0.18-μm CMOS製程，從量測結果來看，輸出頻率24.63-25.18 GHz，輸出功率大於-14 dBm，主動埠消耗功率為7.44 mW，相位雜訊在頻率24.6 GHz為-108.4 dBc/Hz@1 MHz，FOM為-188 dBc/Hz。使用基板偏壓之60-GHz寬頻除頻器採用TSMC 0.13-μm CMOS製程，操作電壓0.7 V時，消耗功率為3.93 mW，量測除頻範圍為53-61.68 GHz，最低除頻靈敏度為-28 dBm@58 GHz。除頻後的相位雜訊為-127 dBc/Hz@1 MHz，輸出功率在可除範圍內皆大於-11 dBm，最大輸出功率為-3 dBm。
24-GHz並聯式除三除頻器採用TSMC 0.18-μm CMOS製程，可降低高頻鎖相迴路的複雜度，操作電壓在0.9 V時消耗功率為8.28 mW，量測除頻範圍為21.7-25 GHz，最低除頻靈敏度量測時為-30 dBm@23.4 GHz。輸入24 GHz除頻後的相位雜訊為-141 dBc/Hz@1 MHz，輸出功率在可除範圍內皆大於-12 dBm，最大輸出功率為-8.2 dBm。而改良除三除頻器之電路佈局並設計V-band除三電路，使電路易於後級除頻器的整合，於V-band除三電路的量測結果方面，操作電壓為0.8 V，消耗功率為4.48 mW，可除頻寬為55.7-56.3 GHz。

This thesis presents the design of a 24-GHz CMOS VCO and 24-, 60-GHz frequency dividers. A 24 -GHz low-power CMOS modified Colpitts VCO is implemented by TSMC 0.18-μm CMOS process. A V-band frequency divider adopts the direct injection locked structure is implemented by TSMC 0.13-μm CMOS process. The V-band ILFD uses the body biasing to improve the injection ratio which can increase the frequency locking range. A K-band and a V-band frequency divider use parallel injection and are implemented by TSMC 0.18-μm and 0.13-um CMOS process.

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