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研究生： 吳佳翰
Wu, Chia-Han
論文名稱： 一個可調頻且具溫度與電壓補償之低抖動弛張振盪器
A Frequency Adjustable Low-Jitter Relaxation Oscillator with Temperature and Supply Voltage Compensation
指導教授： 張志文
Chang, Wenson
張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年： 2025
畢業學年度： 113
語文別： 英文
論文頁數： 141
中文關鍵詞： 內嵌式弛張震盪器 、低抖動震盪器 、二階溫度補償 、製程電壓溫度飄移
外文關鍵詞： embedded relaxation oscillators, low jitter oscillators, second-order temperature compensation, process-voltage-temperature (PVT) variations
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    • 本論文提出兩個內嵌式弛張震盪器設計，其除了具有低週期抖動的特性外，在製程、電源電壓與溫度變化的影響下也能保持一定的頻率穩定性。第一個設計是一個單相位輸出內嵌式弛張震盪器，其採用震盪振幅提升技術來降低週期抖動，並採用一階溫度補償、晶片內電壓調節與外部調整技術來克服溫度變化、電壓擾動與製程變異所造成的震盪頻率飄移。量測結果顯示在合理的製程、電源電壓及溫度變動下的震盪頻率飄移都在0.5%以下。
    除了原本所採用的晶片內電壓調節與外部調整技術來克服電壓擾動與製程變異所造成的震盪頻率飄移外，在第二個設計中採用4相位輸出架構來進一步改善時脈抖動，並且使用了二階溫度補償技巧來得到更好的震盪頻率穩定性。佈局後模擬結果顯示在合理的製程、電源電壓及溫度變動下的頻率飄移都在0.1%以下。

    This thesis proposes two embedded relaxation oscillators with low period jitter and a certain level of frequency stability under PVT (process, voltage, and temperature) variations. The first design is a single-phase output embedded relaxation oscillator which adopts oscillation-swing-boosted techniques to reduce period jitter, and uses first-order temperature compensation, on-chip voltage regulation and external trimming to overcome frequency drift caused by temperature changes, voltage fluctuation and process variations, respectively. Measurement results show that frequency deviation remains within 0.5% under reasonable process, supply voltage, and temperature variations.

    In the second design, in addition to the original on-chip voltage regulation and external trimming to overcome the oscillation frequency drift caused by voltage fluctuation and process variation, the second design adopts a quadrature-phase output architecture to further improve period jitter, and uses a second-order temperature compensation technique to obtain better oscillation frequency stability. Post-layout simulation results indicate that frequency deviation is within 0.1% under the same process, supply voltage, and temperature variations.

    摘 要 II Abstract III 致謝 V List of Tables XI List of Figures XII Chapter 1 Introduction 1 1.1 Background of Oscillators 1 1.2 Organization of the thesis 2 Chapter 2 Fundamentals of Oscillators 4 2.1 Barkhausen Criterion 4 2.2 Common Types of Oscillators 6 2.2.1 Ring Oscillators 7 2.2.2 Relaxation Oscillators 9 2.2.3 LC Oscillators 11 2.2.4 Crystal Oscillators 14 2.3 Comparison of Oscillators 16 Chapter 3 A Swing-Boosted Relaxation Oscillator with First-Order Temperature Compensation 18 3.1 Introduction 18 3.2 Challenges of Conventional Relaxation Oscillators 19 3.2.1 PVT Variation Impact on Oscillation Frequency 20 3.2.1.2 Voltage Variation 20 3.2.2 Offset, Noise and Jitter 22 3.3 Swing-Boosted Relaxation Oscillator 27 3.3.1 Derivation of Oscillation Frequency 29 3.3.2 Offset 31 3.3.3 Noise and Jitter 33 3.4 Hysteresis Comparator 39 3.5 First-Order Temperature Compensation 41 3.5.1 Capacitor 42 3.5.2 Comparator 43 3.5.3 Resistor 45 3.6 Voltage Compensation Mechanism 49 3.6.1 Low-Dropout Linear Regulator 49 3.6.2 Reference Voltage Generator 51 3.7 Trimming System 54 3.7.1 Coarse Trim 55 3.7.2 Fine Trim 56 3.8 Design Goal and Pre-layout Simulation Results 57 3.8.1 Design Goal 57 3.8.2 Pre-layout Simulation Results 58 3.9 Chip Layout and Post-layout Simulation Results 67 3.9.1 Chip Layout and Floor Plan 67 3.9.2 Post-layout Simulation Results 69 3.10 Chip Micrograph, PCB and Measurement Results 70 3.10.1 Chip Micrograph and PCB 70 3.10.2 Measurement Setup and Results 71 Chapter 4 A Quadrature-Phase Relaxation Oscillator with 2nd Order Temperature Compensation 81 4.1 Introduction 81 4.2 Quadrature-Phase Swing-Boosted Relaxation OSC 82 4.2.1 Proposed Architecture 82 4.2.2 Inverter-Based Comparator 85 4.3 Voltage Compensation Mechanism 87 4.4 Temperature Compensation Mechanism 88 4.4.1 First-Order Temperature Compensation 88 4.4.2 Second-Order Temperature Compensation 90 4.5 Trimming System 97 4.6 Design Goal and Pre-layout Simulation Results 97 4.6.1 Design Goal 97 4.6.2 Pre-layout Simulation Results 98 4.7 Chip Layout and Post-layout Simulation Results 101 4.7.1 Temperature Effect of Parasitic Parameter 101 4.7.2 Chip Layout and Floor Plan 104 4.7.3 Post-layout Simulation Results 106 4.8 Chip Micrograph, PCB and Measurement Results 106 4.8.1 Chip Micrograph and PCB 107 4.8.2 Measurement Setup and Results 108 Chapter 5 Conclusion and Future Works 118 5.1 Conclusion 118 5.2 Future Works 119 Bibliography 121

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