熱引發應力為影響封裝結構可靠度的一重要因素。矽晶堆疊數目不斷增加下，必須縮短矽晶的厚度及尺寸，這將增加實驗上分析封裝體受力行為的困難度。利用實驗方法量測封裝體受熱所產生之翹曲及應變場分佈可幫助我們了解產品受力行為。本論文使用雲紋干涉儀量測封裝體的變形量。此外，更高精度的相位移技術被發展出，可用以勾勒出更細微區域的應變場分佈概況。它的解析度為傳統干涉儀的八倍或更高，可達到52nm。因此，由雲紋干涉圖像可精確地分析產品的位移與應變量。
本研究主要量測BGA封裝產品受到熱負載下之熱機械變形，包含單晶片構裝、多晶片構裝及案例分析。實驗主軸分為兩個目標：第一為由典型的雲紋圖像獲取產品的平面位移場；第二為發展出相位移技術，拍攝產品的相位移圖，了解產品應力集中或是最具可靠度因素的區域，並計算這些區域的應變場分佈情形，最後，將這些量測數據與有限元素分析法模擬的結果做比對，分析及討論兩者的差異性。
由實驗量測的典型或是高解析度的雲紋干涉條紋的分布可知，不管是單晶片、多晶片構裝，最具可靠度因素的區域來自矽晶角邊、矽晶與矽晶介面及矽晶與基材界面。此外，封膠區域也存在較大的應變量。另一方面，在堆疊型晶片中，有限元素分析模擬的結果往往低估產品存在的翹曲量與應變值，造成低估的原因除了來自模擬程序中許多簡化的假設，另一個可能的原因來自於IC製程中所殘留的翹曲與應變量。
在LGA案例分析中，有限的封裝空間下，矽晶尺寸越來越薄，當產品產生變形時，大的彎曲應力很有可能導致矽晶斷裂；在量測結果顯示，大的剪向應變發生在最上層的矽晶，但更嚴重的正向應變，沿著y方向發生在最底層的矽晶。

Thermally induced stresses play an important role in controlling the structural reliability. As the demand for increased number of stacking dies to shrink die thickness and size, it will increase the difficulty to analyze the behavior of products under thermal loads experimentally. By using experimental methodology, it will help us to analysis the warpage and strain distributions of packages under thermal loads. In this work, the warpage of packages are measured by moiré interferometry. Moreover, high-resolution phase-shifting moiré interferometry system was developed by Paul S. Ho’s group at the University of Texas at Austin to calculate the strain distributions in tiny region. The resolution of moiré interferometry is up to 8 times greater than conventional moiré interferometry, achieves to 52nm. Hence, accurately determine displacements and strains can be determined by moiré interference fringe.
In this study, we focus on measuring the thermal-mechanical deformations of BGA packages, including single-chip packages, multi-chip packages and an example of LGA packages. This study contains two major objectives. The first objective is to obtain in-plane displacement by regular moiré fringes. The second objective is to carry out phase-shifting technique to take phase maps, and we found the stress concentrations in packages that will most critical areas. Finally, we compared the experimental data with simulation results to find the differences between them.
According to experimental results, the most critical issue areas appear to be the die corner、die/die interface and die/substrate interface in both of single-chip or multi-chip packages. This result is got from the moiré fringe distributions in both regular and high-resolution phase maps. Besides, compound region also have larger strain. Furthermore, the FEA results always underestimate the warpage of stacking die packages. These are due to the simplified assumptions in simulation, and the neglects of residual stress and warpage in IC processes are possibly another reason.
In the case of LGA packages, in which die sizes keep going smaller under thinner and lighter packages design, when packages are under thermal loads, it will induce bending stresses, and possibly cause die crack. According to the results of measurement, the upper chip has severe shear strain, but more severe normal strain along y-direction takes place on the bottom chip.

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