在本論文中，我們實現了一個十位元每秒取樣二千萬次的逐漸趨近式類比數位轉換器，此種改良的電路架構解決了傳統逐漸趨近式類比數位轉換器輸入負載太大的缺點，成功降低輸入的電容負載，配合一個節省能源的開關切換方式來降低功率消耗。
本論文中的類比數位轉換器是使用TSMC 0.18-um 1P6M互補金氧半製程下線驗證。核心電路的面積為0.307 mm x 0.335 mm。量測結果顯示在1.8 V的電壓及20 MS/s的取樣頻率下，可達到有效位元數為7.65位元，消耗功率為1.32 mW，而FOM 是328 fJ/conversion-step

This thesis reports the implementation of a 10-bit 20-MS/s successive-approximation (SAR) analog-to-digital converter (ADC). Comparing with conventional SAR ADCs, this ADC adopts a new architecture to reduce the total input capacitance of a differential SAR ADC. In addition, a set-and-down switching method is adopted to reduce the power consumption of the DAC array.
The proposed ADC is fabricated in TSMC 0.18-um 1P6M digital CMOS process. The core occupies 0.307 mm x 0.335 mm active area. The measurement results show that the effective number of bits (ENOB) is 7.65 bits and the power consumption is 1.32 mW at the supply voltage of 1.8 V and the sampling rate of 20 MS/s. As a result, the figure-of-merit (FOM) is 328 fJ/conversion-step.

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