在本論文中，我們將應變矽鍺之P型金氧半場效電晶體與應變矽之N型金氧半場效電晶體製作於同一片晶片上，開發出新式的互補式金氧半場效電晶體。由許多文獻中可以得知，應變矽N型金氧半場效電晶體可以有效地提升電子的漂移率，此外，應變矽鍺P型金氧半場效電晶體可以提升電洞的漂移率。因此，我們各別製作P型與N型電晶體元件結構，如此便可以分別去設計兩者最佳的結構參數。實驗結果顯示，新式的互補式金氧半場效電晶體之結構的確較純矽互補式金氧半場效電晶體有著更佳的直流特性。
可靠度是元件另一個重要的參數。我們也針對矽鍺元件作可靠度分析。我們研究P型場效電晶體的負偏壓溫度效應。負偏壓溫度效應主要是電洞打斷矽與二氧化矽介面的矽氫鍵結，產生介面陷阱進而影響元件的臨限電壓。由於應變矽鍺元件會將大部分的電洞載子侷限在埋藏通道中，降低矽與二氧化矽介面處電洞的濃度。因此矽鍺P型場效電晶體有較小的負偏壓溫度不穩定性效應，也較為適合應用於積體電路。

In this thesis, two novel CMOS architectures that use tensile stress which induced by the Si nitride-capping layer or SiGe virtual substrate, together with the pseudomorphic compressive stress in SiGe layer to improve the drain current of both N- and PMOSFET simultaneously were investigated. The unique advantage of this process flow is that on the same wafer, individual MOSFET performance can be adjusted independently to their optimum due to the separation process for two type devices. It is found that N- and PMOSFET in both novel CMOS architectures achieved better performance, not only higher drain-to-source saturation current but also higher transconductance (gm) than the Si-control devices, thus making this flow show a great flexibility for developing next-generation high-performance CMOS.
Moreover, negative bias temperature instability (NBTI) effect on strained SiGe PMOSFETs was demonstrated. Due to holes primarily confined in the buried SiGe channel and lower hole concentration in the Si surface channel, SiGe PMOSFETs have lower NBTI effect compared with control Si devices. The experimental results show that SiGe devices are better choices for the future ULSI technology.

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