本研究主要是針對重佈線型態(RDL)之晶圓級晶片尺寸構裝(WLCSP)有無球下金屬層(UBM)之結構進行可靠度試驗及有限元素模擬分析。本文採用構裝產品最常使用之上板溫度循環試驗作為可靠度之測試方法，並以ANSYS有限元素軟體分析兩種WLCSP於熱循環負載下之累積黏塑性應變能密度，並以Darveaux之能量基礎理論預測構裝體錫球接點之疲勞壽命，並將模擬值與實驗值作驗證。溫度循環試驗之結果顯示具有UBM層之WLCSP幾乎全數通過可靠度相關規範所要求之1000次循環，然而無UBM層之WLCSP則全數於1000次循環前失效，顯見省略了具有緩衝及接著效果之UBM層對於WLCSP構裝體仍為一有待克服之挑戰。
本文並針對未通過可靠度試驗之無UBM層WLCSP進行改善數值分析，先以田口式方法選定四個可能之影響因子進行熱疲勞壽命之探討，包括晶片厚度、第二絕緣層厚度、絕緣層楊氏模數及熱膨脹係數，結果顯示絕緣層楊氏模數對於疲勞壽命之影響最大，其次為晶片厚度，絕緣層熱膨脹係數亦有些許影響，而第二絕緣層厚度則未有明顯之影響性。其中絕緣層楊氏模數降低及晶片厚度減少皆可有效提升構裝體之疲勞壽命。接著，並針對錫球之形狀變化對疲勞壽命之影響進行研究，以第二絕緣層開口尺寸及錫球高度之變化進行模擬分析，由結果可知將絕緣層開口尺寸加大及錫球高度增加皆可提升疲勞壽命，且絕緣層開口尺寸對於疲勞壽命之影響較錫球高度為大。

In this research, the redistribution (RDL) typed wafer level chip scale packages (WLCSP) with and without under bump metallurgy (UBM) layers are evaluated by reliability test and finite element simulation analysis. The most commonly used reliability test method for packaging, the board-level temperature cycle test (TCT), is adopted and ANSYS finite element software is applied to evaluate the accumulated viscoplastic strain energy density under a cyclic thermal loading, which is further inputted in Darveaux’ energy based model to find the predicted solder joint fatigue life. The simulation results are then compared with the experimental results. The TCT results show that almost all samples of WLCSP with UBM layers pass 1000 cycles, meeting the mandated requirement. The samples of WLCSP without UBM layers all fail before 1000 cycles. It is apparent that omitting the UBM layers which can provide buffer and adhesion effects is still a challenge to be conquered for WLCSP.
The study further focuses on the parametric improvement analysis for the structure of WLCSP without UBM layers which fails the reliability test. The Taguchi method is first applied to evaluate the effects that some potential factors may have on the thermal fatigue life, including chip thickness, the second dielectric layer thickness, Young’s modulus and coefficient of thermal expansion (CTE) of the dielectric layer. The results show that Young’s modulus of the dielectric layer has the greatest effect followed by chip thickness. CTE of the dielectric layer may cause some effect, but the second dielectric layer thickness has insignificant effect. Both lowering the Young’s modulus of the dielectric layer and thinning the chip can effectively enhance the fatigue life of the package. Furthermore, the effects of solder ball shapes to the fatigue life are also studied. The second dielectric layer opening size and solder ball height are selected for parametric analysis, and the results indicate that a larger opening size and a higher ball can both enhance the solder joint fatigue life, and the effect of opening size is greater than that of ball height.

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