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研究生: 方楷文
Fang, Kai-Wen
論文名稱: 應用於V頻段收發機之氮化鎵倍頻器與CMOS環形混頻器之研製
Development of GaN frequency multiplier and CMOS ring mixer for V-band transceiver
指導教授: 王永和
Wang, Yeong-Her
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2023
畢業學年度: 111
語文別: 英文
論文頁數: 101
中文關鍵詞: 倍頻器混頻器弱反轉諧波抑制次臨界電流緩衝放大器GaN HEMTCMOS
外文關鍵詞: Frequency multiplier, Mixer, Weak-inversion, Harmonic rejection, Subthreshold current, Buffer amplifier, GaN HEMT, CMOS
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  • 現代無線通訊系統中,頻率轉換電路扮演著關鍵角色,其對於發展高頻和低功耗性能至關重要。本論文主要聚焦於V頻帶,實施頻率轉換電路的研製,該研究可分為兩個部分。第一部分,使用GaN on SiC 0.25um HEMT製程,提出了三個電路:頻率三倍頻器、緩衝放大器以及整合電路。頻率三倍頻器的操作頻率範圍為40.2-42.9 GHz,轉換損耗為19.2 dB。三次諧波對於基頻的諧波抑制量大於16 dBc,對二次諧波的抑制量最大可至7 dBc。晶片面積為1.5mm2,功率消耗為70.5 mW。整合了緩衝放大器的電路在操作頻率介於41.1 GHz - 43.8 GHz之間,轉換損耗為22.5 dB。三次諧波對二次諧波和基頻的抑制量分別提高到25 dBc和33 dBc。晶片面積為3mm2,電路功率消耗為454.7 mW。第二部分,使用90 nm CMOS製程實現了混頻器電路,並採用雙平衡式電路架構。將電晶體偏壓在弱反轉區,利用次臨界電流操作電晶體以降低整體電路功耗。該混頻器電路的晶片面積為0.856mm2,轉換增益為3.81 dB。LO驅動功率為-7 dBm。RF頻寬範圍在56.67-60.53 GHz。LO to IF 的隔離度為22.66 dB。LO to RF 的隔離度為16.9 dB。RF to IF 的隔離度為28.9 dB。

    In modern wireless communication networks, frequency conversion circuits represent a key factor in the development of high-frequency and low-power performance. This thesis focuses on the development of frequency conversion circuits in V-band, and the research can be divided into two parts. In the first part, the circuit is implemented by using GaN on SiC 0.25um HEMT process. I present three circuits: a frequency tripler, a buffer amplifier, and an integrated circuit. The frequency tripler operates in the frequency range of 40.2-42.9 GHz with a conversion loss of 19.2 dB. The harmonic rejection of the third harmonic is greater than 16 dBc for the fundamental frequency and up to 7 dBc for the second harmonic. The chip area is 1.5 mm2. Power consumption is 70.5 mW. The integrated circuit operates between 41.1 GHz and 43.8 GHz with a conversion loss of 22.5 dB. The rejection of the third harmonic to the second harmonic and the fundamental frequency is increased to 25 dBc and 33 dBc, respectively, and the circuit power consumption is 454.7 mW. And a chip area of 3 mm2. In the second part, the mixer circuit is implemented using the process of 90 nm CMOS and a double-balanced circuit architecture. The transistors are biased at the weak inversion region, and subthreshold current is used to operate the transistors to reduce the overall circuit power consumption. The mixer circuit has a die area of 0.856 mm2 and a conversion gain of 3.81 dB. the local oscillator drive power is -7 dBm. And the radio frequency bandwidth ranges from 56.67 to 60.53 GHz. The LO to IF isolation is 22.66 dB. And the LO to RF isolation is 16.9 dB. And the RF to IF isolation is 28.9 dB.

    中文摘要 I Abstract III 誌謝 V CONTENTS VIII List of Tables XII List of Figures XIII Chapter 1 Introduction 1 1.1 Research Background 1 1.2 Research Motivation 6 1.3 Chapter Brief 8 Chapter 2 Basic Theory and Parameter Concepts 11 2.1 Transceiver Topology 11 2.1.1 Heterodyne Receiver 15 2.1.2 Homodyne Receiver 16 2.2 Basic Parameters of Frequency Multiplier 17 2.2.1 S-Parameter 17 2.2.2 Conversion Gain/Loss 19 2.2.3 P1dB 20 2.2.4 Harmonic Spectrum 21 2.2.5 Harmonic Suppression 22 2.3 Basic Parameters of Mixer 22 2.3.1 Isolation 22 2.3.2 IP3 23 2.3.3 Intermodulation Distortion (IMD) 24 2.3.4 Noise Figure (NF) 26 Chapter 3 High Harmonic Rejection Frequency Tripler Series Buffer Amplifier Integrated Chip 28 3.1 Overview 28 3.2 Design Principles of Circuits 30 3.2.1 Frequency Tripler 30 3.2.2 Buffer Amplifier 33 3.2.3 Specification 35 3.3 Simulation Results and Layout Verification 36 3.3.1 Frequency Tripler 38 3.3.2 Buffer Amplifier 41 3.3.3 Integrated Chip 44 3.4 Measurement Result 46 3.4.1 Frequency Tripler 46 3.4.2 Buffer Amplifier 54 3.4.3 Integrated Chip 59 3.5 Discussion 68 Chapter 4 A Weak Inversion Ring Mixer for V-Band Application 70 4.1 Overview 70 4.2 Introduction of Mixer Architecture 71 4.2.1 Passive Mixer 71 4.2.2 Double-Balanced Mixer [42][43] 73 4.2.3 Ring Mixer 75 4.3 Mixer Circuit Design Theory 75 4.4 Specification 80 4.5 Simulation Results and Layout Verification 80 4.5.1 Dummy Cell Design 82 4.5.2 Mixer Fully Layout 83 4.5.3 Mixer Simulation Results 84 4.6 Discussion 91 Chapter 5 Conclusions and Future Works 92 5.1 Conclusions 92 5.2 Future Works 94 References 96

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