本論文為設計應用於操控矽量子位元所需低溫高精準度射頻電路。其中包括17.5 GHz升頻混頻器及輸出驅動電路。混頻器以Gilbert Cell基本架構下，使用電流再利用注入式架構，加入PMOS降低開關級電流同時，亦為放大訊號之角色。為維持整體電路線性度與提升增益，混頻器後級接上輸出驅動電路，以簡單的共源極放大器作為基本架構，並採用多閘級電晶體線性之技術。使用Constant-Current作為偏壓電路，透過電流鏡複製電流，製造的偏壓點會隨不同製程、電壓、溫度自動調整，以維持主電路的特性。整體電路使用TSMC 40 nm CMOS製程設計實現。
整合電路先採用On-wafer量測方式，量測結果與佈局模擬結果大致相同。電源供應電壓VDD為1.2V下，整體消耗功率為13.8 mW、整體晶片面積為1.176 mm2。量測結果輸出之射頻端S_22於訊號頻率17.5 GHz下有-16.2 dB的輸出反射損耗。設定輸入訊號PLO為-2 dBm、PIF為-20 dBm條件下，此時轉換增益為3.37 dB、IP1dB約為-8 dBm、IIP3為-0.89 dBm、雜訊指數為12.97 dB，SFDR為34.29 dB。接著為符合低溫量測環境再透過On-PCB量測，需使用印刷電路板以SMA接頭與低溫量測環境相接。低溫(4 K)量測環境下，輸入訊號PLO為-11 dBm、PIF為-40 dBm，晶片於低溫下之轉換增益為-7.64 dB，輸出功率為-47.63 dBm，此結果包含設計之晶片至外接放大器之間經過Balun及接線之損耗。此時扣除LO leakage外，SFDR為34.46 dB由二階失真17 GHz主導。電源供應電壓為1.2V下，整體消耗功率為20.016 mW。

This thesis presents a high linearity CMOS radio-frequency (RF) integrated circuit operated at cryogenic temperature for spin qubits control system. The circuit comprises a 17.5 GHz up-conversion mixer and an output dirver. The current-reused bleeding mixer is based on the Gilbert cell topology, using the transconductor with active load to reduce the bias current through the switch stage. Besides, the PMOS transistor is used as a part of transconductance stage to amplify the input IF signal. In order to maintain the linearity of the whole circuit and achieve moderate conversion gain, integration of the mixer and output driver is proposed. The driver circuit adopts a simple common-source amplifier with multiple gated transistor linearization technique. The constant-current biased circuit can provide the core circuit stable performance over process, voltage, temperature variations via current-mirroring. The whole circuit is implemented in TSMC 40 nm CMOS technology.
Firstly, the on-wafer probing measurement is adopted for the chip, with the results highly close to that of the post-simulation. The chip consumes 13.8 mW from a 1.2 V supply voltage and total chip size including pads is 1.176 mm2. At the 17.5 GHz operation frequency, with the LO power of -2 dBm and the IF power of -20 dBm, the measured S22 is -16.2 dB, the conversion gain is 3.37 dB, the IP1dB is -8 dBm, the IIP¬3 is -0.89 dBm, the noise figure is 12.97 dB and the SFDR is 34.29 dB. So as to meet the low temperature measurement environment, on-PCB measurement with SMA connector is required. With the LO power of -11 dBm and the IF power of -40 dBm, the designed chip achieves a conversion gain of -7.64 dB and an output power of -47.63 dBm when operating at 4 K. Excluding the LO leakage, the SFDR is 34.46 dB, which dominated by second-order distortion tone, 17 GHz. . The whole circuit consumes 20.016 mW from a 1.2 V power supply.

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