本篇論文是對0.35μm製程的p通道橫向擴散金氧半場效電晶體元件(LDMOS transistor)進行熱載子可靠度量測研究。針對各參數的退化，分析出其主要退化的機制。
首先介紹所謂高壓元件的一些結構與一般MOS的差異與應用，以及什麼是LDMOS電晶體。而因應元件微縮，其氧化層厚度和元件尺寸的減少，但其供應電壓卻不會減小，造成漏電流和電場增大。因此其可靠度議題值得深入探討。
經由熱載子實驗量測以求得元件的可靠度分析結果。量測後發現元件的參數在不同的閘極電壓下會有不同的退化機制，然後利用TCAD模擬軟體 (Technology computer-aided design simulation)和charge pumping方法可以找出其退化原因與位置不同所造成不同的結果。
最後經由找出標準尺寸元件的lifetime並且和不同尺寸元件進行熱載子實驗後比較退化有哪些不同。比較lifetime後可以得知改變哪些參數會對於元件可靠度有所改善。

In this thesis, the experiment mainly studies on the hot-carrier reliability of a 0.35 μm p-type lateral double diffusion metal oxide semiconductor field-effect-transistor. Base on the degradation of every parameter, we can analyze the mechanism causing the device degradation.
First, the differences between HV device structure and normal LV MOS structure are introduced. The development of LDMOS device is also introduced. As process scaling down, the reliability becomes an important issue to discuss.
After hot carrier stress experiment on standard dimension device, some parameters under different gate bias result in different degradation trends. TCAD simulation and charge pumping method are used to confirm the damage location induced different degradation.
At last we study on lifetime issue to compare the device reliability. First we need a degradation index in lifetime model. And then we process hot carrier stress experiment on different dimension devices (S, L, and C). Then the extracted lifetime results are compared to find out which dimension variation will improve the device reliability.

[1] C. Contiero, P. Galbiati, and M. Palmieri, “Characteristics and applications of a 0.6μm Bipolar-CMOS-DMOS technology combing VLSI nonvolatile memories,” IEDM Tech. Dig., pp. 465 (1996).
[2] C.Y. Tsai et al., “16-60V Rated LDMOS Show Advanced Performance in a 0.72 um Evolution BiCMOS Power Technology”, in Proc. IEEE IEDM, p367-370, (1997).
[3] V. Parthasarathy, et al., “A 33 V, 0.25 mΩ*cm2 n-channel LDMOS in a 0.65 μm smart-power technology for 20-30 V operation,” ISPSD, pp. 61-64 (1998).
[4] A. Moscatelli, A. Merlini, G. Croce, P. Galbiati, and C. Contiero, “LDMOS implementation in a 0.35μm BCD technology (BCD6),”ISPSD, pp.323, (2000).
[5] T. Terashima, et al., “Multi-voltage device integration technique for 0.5μm BiCMOS and DMOS process,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 331-334 (2000).
[6] Y. Kawagushi, et al., “0.6 μm BiCMOS-based 15 and 25 V LDMOS for analog applications,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 169-172 (2001).
[7] P. Moens, et al., “I3T80: A 0.35 μm based system-on-chip technology for 42 V battery automotive applications,” in Proc. Int. Symp. Power Semiconductor Dev., pp. 225-228 (2002).
[8] Adriaan W. Ludikhuize, “Performance and Innovative Trends in RESURF”, ESSDERC 2001, pp.35-44, (2001).
[9] J. A. Appeals, and H. M. J. Vaes, “High-voltage thin layer devices (RESURF devices)”, IEDM Tech. Dig., pp.238-239, (1979).
[10] A. W. Ludikhuize, “Review of Resurf Technology”, in Proc. IEEE ISPSD, p11-18, (2000).
[11] S.M. Sze, “Physics of Semiconductor Device,” Wiley (1981).
[12] Jun Wang, Rui Li, Yemin Dong, Xin Zou, Li Shao and W.T. Shiau “Substrate current characterization and optimization of high voltage LDMOS transistors” Vol. 52, Issue 6, pp. 886-891, (2008).
[13] K. S. Tian, J. F. Chen, S. Y. Chen, K. M. Wu, J. R. Lee, T. Y. Huang, C. M. Liu, S. L. Hsu, “An Investigation on Hot-Carrier Reliability and Degradation Index in Lateral Diffused Metal-Oxide-Semiconductor Field-Effect Transistors” Japanese Journal of Applied Physics, Vol. 47, Issue 4, pp. 2641, (2008).
[14] Ben G. Streetman, Sanjay Banerjee, “Solid state electronic device,” 5thed, Prentice Hall (2000).
[15] Yuan Taur, Tak h. Ning, ”Fundamentals of modern VLSI devices,” Cambridge, (1998).
[16] A.W. Ludikhuize, “Kirk effect limitations in high voltage IC’s,” Proc. Int. Symp. Power Semiconductor Dev., pp.249, (1994).
[17] 國立成功大學論文 “Development and Hot-Carrier Reliability Study of Integrated High-Voltage MOSFET Transistors,” Kuo-Ming Wu.
[18] Koyanagi, M.; Lewis, A.G.; Zhu, J.; Martin, R.A.; Huang, T.Y.; Chen, J.Y. “Investigation and reduction of hot electron induced punchthrough (HEIP) effect in submicron PMOSFETs” Electron Devices Meeting, International,Vol. 32, p722 – 725, (1986).
[19] K. H. Kwak, J. H. Jang et al. “Suppression of Hot-Electron-Induced Punchthrough on Buried- Channel pMOSFETs with 0.15-μm Gate Lengths” Journal of the Korean Physical Society, Vol. 44, No.1, pp.103-107, (2004).
[20] Dieter K. Schroder, “Semiconductor Material and Device Characterization,” second edition, (1998).
[21] C. C. Cheng, K. C. Tu, and Tahui Wang, “Investigation of Hot Carrier Degradation Modes in LDMOS by Using A Novel Three-region Charge Pumping Technique,” IEEE IRPS, pp. 334-337, (2006).
[22] C. C. Cheng, J. F. Lin, T. Wang, T. H. Hsieh, J. T. Tzeng, Y. C. Jong, R. S. Liou, S. C. Pan, and S. L. Hsu, “Physics and characterization of various hot-carrier degradation modes in LDMOS by using a novel three-region charge pumping technique,” IEEE TDMR, vol. 6, NO. 3, pp. 358-362, (2006).
[23] F. Bauwens, “Locating hot carrier injection in n-type DeMOS transistor by Charge Pumping and 2D device simulations,” Microelectronics Reliability 44, pp.1625-1629, (2004).
[24] M. Sellami, “A Three-Level Charge Pumping Model for Submicronic MOSFET Interface Defaults Simulation,” Internationa1 Conference on Solid Dielectrics, Toulouse, France, July 5-9, (2004).
[25] P. Moens, G. Van den bosch1 and M. Tack “Hole Trapping and de-Trapping Effects in LDMOS Devices under Dynamic Stress,” IEEE IEDM, pp.1-4, (2006).
[26] S. Y. Chen, J. F. Chen, K.M. Wu, J. R. Lee, C. M. Liu, and S. L. Hsu “Effect of Gate Voltage on Hot-Carrier-Induced On-Resistance Degradation in High-Voltage n-Type Lateral Diffused Metal–Oxide–Semiconductor Transistors, ”Jpn. J. Appl. Phys. 47 pp. 2645-2649, (2008).
[27] Chen, JF; Wu, KM; Lee, JR, et al. “Characteristics and improvement in hot-carrier reliability of sub-micrometer high-voltage double diffused drain metal-oxide-semiconductor field-effect transistors,” JAPANESE JOURNAL OF APPLIED PHYSICS, Vol. 46, Issue: 4B, pp 2019-2022. (2007).
[28] J. F. Chen, K. S. Tian, S. Y. Chen, et al., “Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide-semiconductor transistors,” APPLIED PHYSICS LETTERS, Vol. 92, Issue: 24, Article Number: 243501(2008).
[29] C. Y. Chang and S. M. Sze, “ULSI Technology,” (1996).