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研究生： 陳忠和
Chen, Zhong-Ho
論文名稱： 應用於嵌入式即時系統之可移植數位訊號處理器發展環境
Portable DSP Development Environment for Embedded Real-time System
指導教授： 蘇文鈺
Su, W.Y Alvin
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 英文
論文頁數： 63
中文關鍵詞： 數位訊號處理器 、發展環境 、除錯電路 、嵌入式即時系統
外文關鍵詞： Debugging Circuit, SoC, DSP, Development Environment, Embedded System
相關次數： 點閱：91  下載：4 
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    • 　　近年來，有越來越多在嵌入式即時系統(Embedded Real-time System)上的應用，例如數位相機、手機、可攜式多媒體播放器，一般的微處理器(General Purpose Microcontroller)在多媒體的處理上已經不能滿足這些應用；由於數位訊號處理器(Digital Signal Processor)在資料的運算速度的優勢，使得它在消費性電子產品上佔有不可抹滅的地位。本論文的第一部份即描述了如何設計了一個數位訊號處理器，並且將即時作業系統移植到這個數位訊號處理器。通訊能力在嵌入式即時系統中也越來越重要，因此本論文也描述了如何將乙太網路媒體存取控制器(10/100 Ethernet MAC)加入整個系統之中。
    　　發展環境在產品開發過程中扮演相當重要的角色，它可以協助系統開發整除錯，並且縮短開發時間，傳統數位訊號處理器為了增加除錯的能力，必須額外設計新的硬體電路來配合開發環境計，在系統開發初期，這會是一項非常大的負擔，因為本論文第二部份提出了一套可以適用在各種數位訊號處理器的除錯電路設計方法，這個方法可以大大縮短開發發展環境的時間。

    　Recently, there are many applications built around embedded systems such as digital camera, cell phone, portable media player, smart phone, PDA and so on. Most of them require heavy computation. General processors no longer meet the requirement of multimedia applications due to reasons such as cost, power consumption and performance. Because of the ability of dealing with mathematical operations and the relatively simple architectures, digital signal processors (DSP) are now playing the key role in consumer electronics and/or embedded systems. In this thesis, implementation of a DSP is described in detail. A real-time OS is ported on the proposed DSP, too. Since communication is also an important issue in many applications, the presented DSP will combine a 10/100 Ethernet MAC and run TCP/IP protocol.
    　During early development period, a Development Environment is also important. It can shorten the time to market. In order to provide the debugging ability of a new DSP, traditionally, it takes a lot of effort to design a hardware circuit for debugging purpose. In this thesis, we propose a method to design a debugging circuit which suites to varied DSP. By applying this method, it shortens the time to design a development environment.

    CONTENTS 1 1 INTRODUCTION 4 1.1 MOTIVATION 4 1.2 THESIS ORGANIZATION 5 2 BACKGROUND 7 2.1 MICROPROCESSOR ARCHITECTURES 7 2.1.1 Computer Applications 7 2.1.2 Typical Computer Architectures 8 2.1.3 SCREAM DSP Architecture 9 3 SCREAM DSP ARCHITECTURE 12 3.1 COMPUTATIONAL UNITS 12 3.1.1 Data Format 12 3.1.2 Arithmetic Logic Unit (ALU) 13 3.1.3 MAC 17 3.1.4 SHT 22 3.2 DATA ADDRESS GENERATOR (DAG) 26 3.2.1 DAG Operations 26 3.2.2 DAG Modes 27 3.3 MEMORY 27 3.3.1 Overview 27 3.3.2 Memory Map 28 3.4 TIMER 29 3.4.1 Overview 29 3.4.2 Operations 29 4 REAL TIME OPERATION SYSTEM 32 4.1 ΜC/OS-II INTRODUCTION 32 4.2 PORTING ΜC/OS-II 32 4.2.1 Processor Requirement 32 4.2.2 Processor Depend Code 33 5 ETHERNET 34 5.1 ETHERNET MAC 34 5.2 UIP TCP/IP PROTOCOL 34 6 DEVELOPMENT ENVIRONMENT 36 6.1 OVERVIEW 36 6.2 DEBUGGING ARCHITECTURE 37 6.3 DEBUGGING OPERATION 40 6.4 SOFTWARE USER INTERFACE 40 7 EXPERIMENT RESULTS 42 7.1 SCREAM DSP16 42 7.2 DEVELOPMENT ENVIRONMENT 42 7.3 APPLICATION 43 7.4 SUMMARY 44 8 FUTURE WORKS 45 9 REFERENCE 46 A SCREAM DSP16 IP CORE 47 A.1 INTRODUCTION 47 A.2 FEATURES 47 A.3 DIRECTORY STRUCTURE 48 B DSP2191 IP CORE 50 B.1 OVERVIEW 50 B.1.1 ALU 50 B.1.2 MAC 50 B.1.3 SHT 51 B.1.4 DAG 51 B.1.5 PSQ 51 B.1.6 TIMER 51 B.1.7 Memory Controller 51 B.1.8 DMA Controller 51 B.1.9 Wishbone Master and Slave 52 C DESCRIPTION OF CORE MODULES 53 C.1.1 ALU module (alu.v) 53 C.1.2 MAC module (mac.v) 54 C.1.3 SHT module (sht.v) 56 C.1.4 Functional Unit bus 57 C.1.5 DAG module (dag.v) 58 C.1.6 Program Sequencer (psq.v) 59 C.1.7 Timer module (timer.v) 62 C.1.8 Memory Controller module (memctrl.v) 62 C.1.9 Memory Block module (memblock.v) 63 C.1.10 Wishbone Interface 63

    [1] John L. Hennessy & David A. Patterson, “Computer Architectures Third Edition“, CA, USA: Morgan Kaufmann Publishers, 2003
    [2] Vijay K. Madisetti, “VLSI Digital Signal Processors,” MA USA: Butterworth-Heinemann, 1995
    [3] IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Computer Society, New York, 1990
    [4] Ing-Jer Huang and Chung-Fu Kao, “Exploration of Multiple ICE’s for Embedded Microprocessor Cores in an SOC”, The Asia-Pacific Conference on ASIC, 2000
    [5] Analog Device web sit, http://www.analog.com
    [6] ARM web site, http://www.arm.com
    [7] OPENCORE.ORG, “Specification for the WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Core, Revision: B.3”, 2002
    [8] Igor Mohor, “Ethernet IP Core Specification Rev. 1.19”, 2002
    [9] Jean J. Labrosse, “MicroC OS II: The Real Time Kernel”, CMP Books, 2nd Bk&Cdr edition, 2002
    [10] Yervant Zorian, Erik Jan Marinissen and Sujit Dey, “Testing Embedded-Core-Based System Chips”, IEEE Computer Society, Vol. 32, No. 6, pp. 52-60, June 1999

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