在現代晶片設計中，電源消耗已成為一嚴重的問題。為處理此問題，多重動態供電壓設計被提出，且被視為在現代晶片中的有效解決方案；然而，在電源模式切換間所產生的時序差問題，增加了在多重動態供電壓設計中減低時序差的複雜度。在本篇論文中，我們提出了一個由負載平衡時鐘樹合成，並結合可調整式緩衝器插入方案，來解決多重動態供電壓設計下的時序差問題。本時鐘樹合成器採用了最小擴張樹來進行繞線長估計，並用以進行以圖形理論為底之叢集建立；當初始的時鐘樹完成時，階級式緩衝器將會插入以減低時序延遲，之後再插入可調整式緩衝器以解決多重動態供電壓設計下的時序差問題。可調整式緩衝器可用來產生多餘的延遲，因此可用以調整時鐘樹中的時序延遲與時序差。我們提出了一個有效的可調整式緩衝器插入演算法，其可減低時序差、額外消耗面積與運算時間；與之前最佳的可調整式緩衝器插入演算法比較，實驗結果顯示我們可減少最高 42.40% 的額外消耗面積，並達到最高 117.84 倍的運算時間提升。

Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, multiple dynamic supply voltage (MDSV) designs are proposed as an efficient solution in modern IC designs. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this paper, we propose a load-balanced clock tree synthesizer with adjustable delay buffer (ADB) insertion for the minimization of clock skew in MDSV designs. The clock tree synthesizer adopts the minimum spanning tree (MST) metric to estimate the interconnect capacitance and execute the graph-theoretic clustering. Once the initial clock tree construction is complete, the leveled buffers are inserted for clock latency reduction. Then the ADBs with delay value assignments are inserted to reduce clock skew in MDSV designs. The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm of ADB insertion, experimental results show maximum 42.40% area overhead improvement and 117.84 times runtime speedup.

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