簡易檢索 / 詳目顯示

研究生: 李濬譯
Lee, Chun-Yi
論文名稱: 改善深次微米雙鑲嵌結構碳化矽氮與銅導線/低介電絕缘層界面之研究
Technology to improve the interface reliability of SiCN and Cu/low k dielectrics for deep submicron dual damascene scheme
指導教授: 方炎坤
Fang, Yean-Kuen
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系碩士在職專班
Department of Electrical Engineering (on the job class)
論文出版年: 2006
畢業學年度: 94
語文別: 英文
論文頁數: 56
中文關鍵詞: 碳化矽氮界面低介電絕缘層
外文關鍵詞: SiC, Low k, SiCN, Interface
相關次數: 點閱:120下載:7
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 絕緣體/擴散阻隔層有兩個主要功能:第一、它必須有適當的蝕刻選擇比,相對於金屬間介電層;第二、它也同時扮演著銅導線的頂覆蓋層。因此擴散阻隔層應該有適度的附著及介面特性以滿足電子遷移的須求。絕緣體/擴散阻隔層也會嚴重的影響到整體的有效介電常數,所以它的厚度與介電常數必須盡可能的降低。
    為了降低導線間傳輸的延遲,降低絕緣體/擴散阻隔層的介電常數,成了繼銅導線暨低介電材質外,下一步被導入至高速元件製作,因此碳化矽及其衍生物:如碳化矽氮以及碳化矽氧;被廣泛的研究來取代氮化矽,成為九十奈米以下的製程的不二之選。然而它卻也引發兩個新的介面問題,其一為碳化矽與銅導線的介面問題,另一為碳化矽與低介電材質的介面問題。前者會降低導線的電子遷移的特性,而後者則與導線之間絕緣體的崩潰有極為密切的關連。
    在這篇論文中,我們將會專注在碳化矽與低介電材質特性之研究,並從中發現“預熱”這個步驟的存在及順序,將影響到介面的特性。經過“預熱”製程以及碳化矽層的改善,相較於未經過“預熱”製程,更可以有效改善漏電流的特性。再者,較長時間的“預熱”,可以得到較佳的絕緣體崩潰表現,但在“氨預處理”後的“預熱”,卻無法改善絕緣體崩潰電壓的表現。我們認為這個差異是來自於苯駢三氮唑的存在,苯駢三氮唑被廣泛使用在化學機械研磨製程中,當成銅的緩腐劑,並且可藉由加熱的步驟使之蒸發,然卻會被“預處理”的氨電漿轉換成另外一種雜質,進而無法讓接下來的“預熱”這個步驟所去除。

    The dielectric/diffusion barrier has two main functions; one, it must have adequate etch selectivity with respect to the via dielectric layer so that etching of the underlying IMD adjacent to non-landed vias is avoided. Another, it serves as the cap layer for the underlying Cu wiring layer. Hence the diffusion barrier should have acceptable adhesion and interface properties to meet the Cu electromigration requirements. The dielectric/diffusion barrier can also be a significant contributor to overall keff so its thickness and k value (dielectric constant) should both be minimized.
    To reduce RC delay of interconnects, reducing the k value of dielectric/diffusion barrier is the next step after Cu and IMD low-k material were introduced in the fabrication of fast speed devices. Therefore, SiC and its derivatives (SiCN and SiCO) have been studied widely as the alternatives of Silicon Nitride on 90nm and beyond. However, it also creates two new interfaces; one is between SiC and Cu and the other is between SiC and low-k. The former will contribute to the electron migration property of interconnects and the later is tied up with the dielectric property of isolation from metal line to metal line.
    In this thesis, we have concentrated one subject on the interface property of SiC/low-k and found that the presence of “heat-up” and its sequence will affect the interface property. The “Heat-up first” before ammonia pre-treatment and combined with the bulk film improvement can improve the leakage performance one order than the “pre-treatment first” approach. Moreover, longer time of “heat-up” before pre-treatment also suggests higher breakdown voltage but longer time “heat-up” after pre-treatment cannot improve the breakdown voltage. We attribute the difference to the presence of BTA (Benzotriazole, C6H5N3), which is intensively used as Cu corrosion inhibitor in CMP (Chemical Mechanical Polish) process and can be vaporized in the “heat-up” step but could turn into impurity by the presence of ammonia plasma in pre-treatment step and hence cannot be removed by following degassing step.

    Abstract (Chinese)...........V Abstract.....................VII Acknowledgement..............IX Table of Contents............XI Tables Captions..............XIII Figures Captions.............XIII Chapter 1 Introduction.............1 Chapter 2 Hypothesis and mechanism of SiC/low-k dielectric interface breakdown...........5 Chapter 3 Experiments..................8 3-1 SiC bulk film enhancement............8 3-2 SiC/low-k dielectric interface optimization.......10 3-3 SiC/copper interface verification...........15 3-4 SiC/low-k dielectric interface analysis..........16 Chapter 4 Results and discussions...........17 4-1 Eletrical performance ............17 4-1.1 Comparison of with and without “heat-up”....................17 4-1.2 Comparison of different duration of “heat-up”................17 4-1.3 Comparison of “heat-up first” and “pre-treatment first”.................18 4-1.4 Comparison of different duration of “pre-treatment”......................18 4-2 Surface and interface analysis............19 Chapter 5 Conclusion and prospect ............21 Reference ................23

    [1] Kinya Goto, Hiroshi Yuasa, Akira Andatsu, and Masazumi Matsuura, “ Film Characterization of Cu Diffusion Barrier Dielectrics for 90nm and 65nm Technology Node Cu Interconnects”, 2003 IEEE.
    [2] Albert S. Lee, Annamalai Lakshmanan, Nagarajan Rajagopalan, Zhenjiang Cui, Maggie Le, Li Qun Xia, Bok Heon Kim, and Hichem M’Saad, “Reliability of Dielectric Barriers in Copper Damascene Applications”, 2003 IEEE.
    [3] T. Usui, T. Oki, H. Miyajima, K. Tahuchi, K. Watanabe, T. Hasegawa and H. Shibata, “Identification of Electromigration Dominant Diffusion Path for Cu damascene interconnects and Effect of Plasma Treatment and Barrier Dielectrics on Electromigration Performance”, 2004 IEEE Annual International Reliability Physics Symposium, P.246 – 250.
    [4] Young Jin Wee, Soo Geun Lee, Won Sang Song, Kyoung-Woo Lee, Nam Hyung Lee, Ja Eung Ku, Ki-Kwan Park, Seung Jin Lee, Jae Hak Kim, Joo Hyuk Chung, Hong Jae Shin, San Rok Hah, Ho-Kyu Kang, Gwang Pyuk Suh, “Alleviating Electromigration Through Re-Engineering The Interface Between Cu & Dielectric-Diffusion-Barrier in 90nm Cu/SiOC (k=2.9) Device”, 2003 IEEE
    [5] T. Yoshie, K. Yoneda, N. Ohashi and N. Kobayashi, “TDDB degradation analysis using Ea of leakage current for reliable porous CVD SiOC (k=2.45)/Cu interconnects”, 2004 IEEE
    [6] Masayuki Tanaka, Shigehiko Saida, Tadashi Iijima and Yoshitaka Tsunashima, “Low-k SiN film for Cu interconnects integration fabricated by ultra low temperature thermal CVD”, 1999 Symposium on VLSI technology digest of technical paper
    [7] S. Deshpande, S.C. Kuiry, M. Klimov, and S. Seal, “Elucidating Cu-Glycine and BTA Complexations in Cu-CMP using SIMS and XPS”, 2005 Electrochemical and Solid-State Letters
    [8] Nobuhiro Konishi, Youhei Yamada, Junji Noguchi, Tomoko Jimbo and Osamu Inoue, “Influence of CMP process on defects in SiOC films and TDDB reliability”, 2005 IEEE
    [9] C. Guedj, V. Arnal, J.F. Guillaumond, L. Arnaud, J.P. Barnes, A. Toffoli, V. Jousseaume, A. Roule, S. Maitrejean, L.L. Chapelon, G. Reimbold, J. Torres, G. Passemard, “Influence of the diffusion barriers on the dielectric reliability of ULK/Cu advanced interconnects”, 2005 IEEE
    [10] Zhe Chen, Krishnamachar Prasad, Chaoyong Li, Ning Jiang, and Dong Gui, “Investigation of Dielectric/Metal Bilayer Sidewall Diffusion Barrier for Cu/Porous Ultra-Low-k Interconnects”, 2005 IEEE Transactions on device and materials reliability vol.5
    [11] Hiroshi Okamura and Shinichi Ogawa, “Low damage via formation with low resistance by NH3 thermal reduction for Cu / Ultra low-k Interconnects”, 2004 IEEE
    [12] R. Gonella, P. Motte, J. Torres, “Time-dependent-dielectric breakdown used to assess copper contamination impact on inter-level dielectric reliability”, 2000 IEEE

    下載圖示 校內:2008-08-28公開
    校外:2008-08-28公開
    QR CODE